dclr              759 drivers/edac/amd64_edac.c static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
dclr              761 drivers/edac/amd64_edac.c 	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
dclr              774 drivers/edac/amd64_edac.c 		    (dclr & BIT(19)) ? "yes" : "no");
dclr              778 drivers/edac/amd64_edac.c 		 (dclr & BIT(8)) ?  "enabled" : "disabled");
dclr              782 drivers/edac/amd64_edac.c 			 (dclr & BIT(11)) ?  "128b" : "64b");
dclr              785 drivers/edac/amd64_edac.c 		 (dclr & BIT(12)) ?  "yes" : "no",
dclr              786 drivers/edac/amd64_edac.c 		 (dclr & BIT(13)) ?  "yes" : "no",
dclr              787 drivers/edac/amd64_edac.c 		 (dclr & BIT(14)) ?  "yes" : "no",
dclr              788 drivers/edac/amd64_edac.c 		 (dclr & BIT(15)) ?  "yes" : "no");
dclr             1349 drivers/edac/amd64_edac.c 	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
dclr             1353 drivers/edac/amd64_edac.c 		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
dclr             1516 drivers/edac/amd64_edac.c 	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
dclr             1521 drivers/edac/amd64_edac.c 		return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
dclr             1523 drivers/edac/amd64_edac.c 		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);