dclk_min_div       79 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	for (i = tcon->dclk_min_div; i <= tcon->dclk_max_div; i++) {
dclk_min_div      119 drivers/gpu/drm/sun4i/sun4i_rgb.c 	tcon->dclk_min_div = 6;
dclk_min_div      343 drivers/gpu/drm/sun4i/sun4i_tcon.c 	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
dclk_min_div      412 drivers/gpu/drm/sun4i/sun4i_tcon.c 	tcon->dclk_min_div = 7;
dclk_min_div      491 drivers/gpu/drm/sun4i/sun4i_tcon.c 	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
dclk_min_div     1428 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 4,
dclk_min_div     1435 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 4,
dclk_min_div     1444 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 1,
dclk_min_div     1452 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 1,
dclk_min_div     1458 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 4,
dclk_min_div     1466 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 1,
dclk_min_div     1472 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 1,
dclk_min_div     1486 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 1,
dclk_min_div     1492 drivers/gpu/drm/sun4i/sun4i_tcon.c 	.dclk_min_div		= 1,
dclk_min_div      227 drivers/gpu/drm/sun4i/sun4i_tcon.h 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
dclk_min_div      251 drivers/gpu/drm/sun4i/sun4i_tcon.h 	u8				dclk_min_div;