dclk             4507 arch/x86/events/intel/uncore_snbep.c 	INTEL_UNCORE_EVENT_DESC(dclk,		"event=0xff,umask=0x10"),
dclk               49 drivers/clk/hisilicon/clkdivider-hi6220.c 	struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
dclk               51 drivers/clk/hisilicon/clkdivider-hi6220.c 	val = readl_relaxed(dclk->reg) >> dclk->shift;
dclk               52 drivers/clk/hisilicon/clkdivider-hi6220.c 	val &= div_mask(dclk->width);
dclk               54 drivers/clk/hisilicon/clkdivider-hi6220.c 	return divider_recalc_rate(hw, parent_rate, val, dclk->table,
dclk               55 drivers/clk/hisilicon/clkdivider-hi6220.c 				   CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
dclk               61 drivers/clk/hisilicon/clkdivider-hi6220.c 	struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
dclk               63 drivers/clk/hisilicon/clkdivider-hi6220.c 	return divider_round_rate(hw, rate, prate, dclk->table,
dclk               64 drivers/clk/hisilicon/clkdivider-hi6220.c 				  dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
dclk               73 drivers/clk/hisilicon/clkdivider-hi6220.c 	struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
dclk               75 drivers/clk/hisilicon/clkdivider-hi6220.c 	value = divider_get_val(rate, parent_rate, dclk->table,
dclk               76 drivers/clk/hisilicon/clkdivider-hi6220.c 				dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
dclk               78 drivers/clk/hisilicon/clkdivider-hi6220.c 	if (dclk->lock)
dclk               79 drivers/clk/hisilicon/clkdivider-hi6220.c 		spin_lock_irqsave(dclk->lock, flags);
dclk               81 drivers/clk/hisilicon/clkdivider-hi6220.c 	data = readl_relaxed(dclk->reg);
dclk               82 drivers/clk/hisilicon/clkdivider-hi6220.c 	data &= ~(div_mask(dclk->width) << dclk->shift);
dclk               83 drivers/clk/hisilicon/clkdivider-hi6220.c 	data |= value << dclk->shift;
dclk               84 drivers/clk/hisilicon/clkdivider-hi6220.c 	data |= dclk->mask;
dclk               86 drivers/clk/hisilicon/clkdivider-hi6220.c 	writel_relaxed(data, dclk->reg);
dclk               88 drivers/clk/hisilicon/clkdivider-hi6220.c 	if (dclk->lock)
dclk               89 drivers/clk/hisilicon/clkdivider-hi6220.c 		spin_unlock_irqrestore(dclk->lock, flags);
dclk              560 drivers/gpu/drm/amd/amdgpu/amdgpu.h 	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
dclk              570 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
dclk               61 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 	u32 dclk;
dclk              163 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 	u32 dclk;
dclk             1335 drivers/gpu/drm/amd/amdgpu/cik.c static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
dclk             1343 drivers/gpu/drm/amd/amdgpu/cik.c 	r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
dclk              920 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
dclk              926 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
dclk              935 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 							 table->entries[i].dclk, false, &dividers);
dclk             2288 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	pi->video_start = new_rps->dclk || new_rps->vclk ||
dclk             2665 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             2668 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		rps->dclk = 0;
dclk             2901 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             3274 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	*equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
dclk              332 drivers/gpu/drm/amd/amdgpu/nv.c static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
dclk             1231 drivers/gpu/drm/amd/amdgpu/si.c static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
dclk             2372 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	    amdgpu_state->vclk && amdgpu_state->dclk)
dclk             3180 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             3187 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
dclk             3198 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             3205 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
dclk             3480 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	if (rps->vclk || rps->dclk) {
dclk             5631 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
dclk             5668 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	if (amdgpu_state->vclk && amdgpu_state->dclk) {
dclk             7117 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             7120 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;
dclk             7123 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		rps->dclk = 0;
dclk             7498 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             7905 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             7977 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	*equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
dclk              605 drivers/gpu/drm/amd/amdgpu/soc15.c static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
dclk              771 drivers/gpu/drm/amd/amdgpu/vi.c static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
dclk              780 drivers/gpu/drm/amd/amdgpu/vi.c 		r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
dclk              788 drivers/gpu/drm/amd/amdgpu/vi.c 		r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
dclk               66 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	struct dm_pp_clock_range dclk;
dclk               59 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h 	uint32_t  dclk;                                              /* UVD D-clock */
dclk              723 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		mm_table_record->dclk = le32_to_cpu(mm_dependency_record->ulDClk);
dclk             1131 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		uvd_table->entries[i].dclk = ((unsigned long)entry->ucDClkHigh << 16)
dclk              792 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
dclk               98 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h 	uint32_t dclk;
dclk             3257 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
dclk             3405 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
dclk             4223 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
dclk               69 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  dclk;
dclk              523 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			(i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
dclk             1387 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
dclk             1690 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
dclk             1736 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				dclk = uvd_table->entries[uvd_index].dclk;
dclk             1737 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				*((uint32_t *)value) = dclk;
dclk              115 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h 	uint32_t dclk;
dclk             1399 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 						dep_mm_table->entries[i].dclk) {
dclk             1401 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					dep_mm_table->entries[i].dclk;
dclk             2065 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			dep_table->entries[i].dclk ==
dclk             3119 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
dclk             4671 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
dclk               97 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	uint32_t  dclk;
dclk              371 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk);
dclk              114 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	uint32_t  dclk;
dclk              132 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	uint32_t dclk;
dclk              218 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	uint32_t			dclk;
dclk              110 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	uint32_t dclk;
dclk              137 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	uint32_t dclk;
dclk              184 drivers/gpu/drm/amd/powerplay/inc/power_state.h 	unsigned long dclk;
dclk              653 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
dclk             1531 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					uvd_table->entries[count].dclk;
dclk             1575 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
dclk             1411 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
dclk             1325 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
dclk             1335 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
dclk              810 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
dclk               14 drivers/gpu/drm/i915/display/intel_bw.c 	u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
dclk               78 drivers/gpu/drm/i915/display/intel_bw.c 	sp->dclk = val & 0xffff;
dclk              110 drivers/gpu/drm/i915/display/intel_bw.c 			      i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
dclk              117 drivers/gpu/drm/i915/display/intel_bw.c static int icl_calc_bw(int dclk, int num, int den)
dclk              120 drivers/gpu/drm/i915/display/intel_bw.c 	return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6);
dclk              125 drivers/gpu/drm/i915/display/intel_bw.c 	u16 dclk = 0;
dclk              129 drivers/gpu/drm/i915/display/intel_bw.c 		dclk = max(dclk, qi->points[i].dclk);
dclk              131 drivers/gpu/drm/i915/display/intel_bw.c 	return dclk;
dclk              195 drivers/gpu/drm/i915/display/intel_bw.c 			bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
dclk             2756 drivers/gpu/drm/radeon/btc_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             2662 drivers/gpu/drm/radeon/ci_dpm.c 			rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
dclk             5462 drivers/gpu/drm/radeon/ci_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             5465 drivers/gpu/drm/radeon/ci_dpm.c 		rps->dclk = 0;
dclk             5965 drivers/gpu/drm/radeon/ci_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             9456 drivers/gpu/drm/radeon/cik.c int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
dclk             9464 drivers/gpu/drm/radeon/cik.c 	r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
dclk             1169 drivers/gpu/drm/radeon/evergreen.c int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
dclk             1180 drivers/gpu/drm/radeon/evergreen.c 	r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
dclk             1184 drivers/gpu/drm/radeon/evergreen.c 	cg_scratch |= (dclk / 100) << 16; /* Mhz */
dclk             1192 drivers/gpu/drm/radeon/evergreen.c int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
dclk             1206 drivers/gpu/drm/radeon/evergreen.c 	if (!vclk || !dclk) {
dclk             1212 drivers/gpu/drm/radeon/evergreen.c 	r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
dclk              838 drivers/gpu/drm/radeon/kv_dpm.c 		pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
dclk              844 drivers/gpu/drm/radeon/kv_dpm.c 			(u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
dclk              853 drivers/gpu/drm/radeon/kv_dpm.c 						     table->entries[i].dclk, false, &dividers);
dclk             2223 drivers/gpu/drm/radeon/kv_dpm.c 	pi->video_start = new_rps->dclk || new_rps->vclk ||
dclk             2597 drivers/gpu/drm/radeon/kv_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             2600 drivers/gpu/drm/radeon/kv_dpm.c 		rps->dclk = 0;
dclk             2857 drivers/gpu/drm/radeon/kv_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             3516 drivers/gpu/drm/radeon/ni_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             3523 drivers/gpu/drm/radeon/ni_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk             3534 drivers/gpu/drm/radeon/ni_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             3541 drivers/gpu/drm/radeon/ni_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk             3905 drivers/gpu/drm/radeon/ni_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             3908 drivers/gpu/drm/radeon/ni_dpm.c 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;
dclk             3911 drivers/gpu/drm/radeon/ni_dpm.c 		rps->dclk = 0;
dclk             4291 drivers/gpu/drm/radeon/ni_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             4319 drivers/gpu/drm/radeon/ni_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk              203 drivers/gpu/drm/radeon/r600.c int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
dclk              221 drivers/gpu/drm/radeon/r600.c 	if (!vclk || !dclk) {
dclk              232 drivers/gpu/drm/radeon/r600.c 	r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
dclk             1162 drivers/gpu/drm/radeon/r600_dpm.c 				rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
dclk             1339 drivers/gpu/drm/radeon/radeon.h 	u32 dclk;
dclk             1425 drivers/gpu/drm/radeon/radeon.h 	u32 dclk;
dclk             1695 drivers/gpu/drm/radeon/radeon.h 				  unsigned vclk, unsigned dclk,
dclk             1960 drivers/gpu/drm/radeon/radeon.h 		int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk              411 drivers/gpu/drm/radeon/radeon_asic.h int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk              478 drivers/gpu/drm/radeon/radeon_asic.h int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk              535 drivers/gpu/drm/radeon/radeon_asic.h int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk              536 drivers/gpu/drm/radeon/radeon_asic.h int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk              749 drivers/gpu/drm/radeon/radeon_asic.h int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk              787 drivers/gpu/drm/radeon/radeon_asic.h int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk              960 drivers/gpu/drm/radeon/radeon_uvd.c 				  unsigned vclk, unsigned dclk,
dclk              975 drivers/gpu/drm/radeon/radeon_uvd.c 	vco_min = max(max(vco_min, vclk), dclk);
dclk              996 drivers/gpu/drm/radeon/radeon_uvd.c 		dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
dclk             1002 drivers/gpu/drm/radeon/radeon_uvd.c 		score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
dclk              573 drivers/gpu/drm/radeon/rs780_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk              579 drivers/gpu/drm/radeon/rs780_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk              590 drivers/gpu/drm/radeon/rs780_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk              596 drivers/gpu/drm/radeon/rs780_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk              730 drivers/gpu/drm/radeon/rs780_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk              733 drivers/gpu/drm/radeon/rs780_dpm.c 		rps->dclk = 0;
dclk              737 drivers/gpu/drm/radeon/rs780_dpm.c 		if ((rps->vclk == 0) || (rps->dclk == 0)) {
dclk              739 drivers/gpu/drm/radeon/rs780_dpm.c 			rps->dclk = RS780_DEFAULT_DCLK_FREQ;
dclk              947 drivers/gpu/drm/radeon/rs780_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk              996 drivers/gpu/drm/radeon/rs780_dpm.c 	seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             1519 drivers/gpu/drm/radeon/rv6xx_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             1525 drivers/gpu/drm/radeon/rv6xx_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk             1536 drivers/gpu/drm/radeon/rv6xx_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             1542 drivers/gpu/drm/radeon/rv6xx_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk             1804 drivers/gpu/drm/radeon/rv6xx_dpm.c 		rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
dclk             1807 drivers/gpu/drm/radeon/rv6xx_dpm.c 		rps->dclk = 0;
dclk             2015 drivers/gpu/drm/radeon/rv6xx_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             2047 drivers/gpu/drm/radeon/rv6xx_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk               49 drivers/gpu/drm/radeon/rv770.c int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
dclk               51 drivers/gpu/drm/radeon/rv770.c int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
dclk               58 drivers/gpu/drm/radeon/rv770.c 		return evergreen_set_uvd_clocks(rdev, vclk, dclk);
dclk               65 drivers/gpu/drm/radeon/rv770.c 	if (!vclk || !dclk) {
dclk               71 drivers/gpu/drm/radeon/rv770.c 	r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
dclk             1439 drivers/gpu/drm/radeon/rv770_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             1445 drivers/gpu/drm/radeon/rv770_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk             1456 drivers/gpu/drm/radeon/rv770_dpm.c 	    (new_ps->dclk == old_ps->dclk))
dclk             1462 drivers/gpu/drm/radeon/rv770_dpm.c 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
dclk             2154 drivers/gpu/drm/radeon/rv770_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             2157 drivers/gpu/drm/radeon/rv770_dpm.c 		rps->dclk = 0;
dclk             2161 drivers/gpu/drm/radeon/rv770_dpm.c 		if ((rps->vclk == 0) || (rps->dclk == 0)) {
dclk             2163 drivers/gpu/drm/radeon/rv770_dpm.c 			rps->dclk = RV770_DEFAULT_DCLK_FREQ;
dclk             2440 drivers/gpu/drm/radeon/rv770_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             2484 drivers/gpu/drm/radeon/rv770_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             6997 drivers/gpu/drm/radeon/si.c int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
dclk             7010 drivers/gpu/drm/radeon/si.c 	if (!vclk || !dclk) {
dclk             7015 drivers/gpu/drm/radeon/si.c 	r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
dclk             2282 drivers/gpu/drm/radeon/si_dpm.c 	    radeon_state->vclk && radeon_state->dclk)
dclk             3021 drivers/gpu/drm/radeon/si_dpm.c 	if (rps->vclk || rps->dclk) {
dclk             5169 drivers/gpu/drm/radeon/si_dpm.c 	if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
dclk             5206 drivers/gpu/drm/radeon/si_dpm.c 	if (radeon_state->vclk && radeon_state->dclk) {
dclk             6717 drivers/gpu/drm/radeon/si_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             6720 drivers/gpu/drm/radeon/si_dpm.c 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;
dclk             6723 drivers/gpu/drm/radeon/si_dpm.c 		rps->dclk = 0;
dclk             7107 drivers/gpu/drm/radeon/si_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk              824 drivers/gpu/drm/radeon/sumo_dpm.c 	radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
dclk              841 drivers/gpu/drm/radeon/sumo_dpm.c 	    (new_rps->dclk == old_rps->dclk))
dclk              859 drivers/gpu/drm/radeon/sumo_dpm.c 	    (new_rps->dclk == old_rps->dclk))
dclk             1415 drivers/gpu/drm/radeon/sumo_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             1418 drivers/gpu/drm/radeon/sumo_dpm.c 		rps->dclk = 0;
dclk             1802 drivers/gpu/drm/radeon/sumo_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             1825 drivers/gpu/drm/radeon/sumo_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             1833 drivers/gpu/drm/radeon/sumo_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk              899 drivers/gpu/drm/radeon/trinity_dpm.c 	if ((rps->vclk == 0) && (rps->dclk == 0))
dclk              912 drivers/gpu/drm/radeon/trinity_dpm.c 	    (rps1->dclk == rps2->dclk) &&
dclk              944 drivers/gpu/drm/radeon/trinity_dpm.c 				radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
dclk              955 drivers/gpu/drm/radeon/trinity_dpm.c 		radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
dclk             1460 drivers/gpu/drm/radeon/trinity_dpm.c 		    (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))
dclk             1694 drivers/gpu/drm/radeon/trinity_dpm.c 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
dclk             1697 drivers/gpu/drm/radeon/trinity_dpm.c 		rps->dclk = 0;
dclk             1937 drivers/gpu/drm/radeon/trinity_dpm.c 			pi->sys_info.uvd_clock_table_entries[i].dclk =
dclk             2020 drivers/gpu/drm/radeon/trinity_dpm.c 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk             2045 drivers/gpu/drm/radeon/trinity_dpm.c 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
dclk               70 drivers/gpu/drm/radeon/trinity_dpm.h 	u32 dclk;
dclk              158 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	struct clk *dclk;
dclk              563 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	ret = clk_enable(vop->dclk);
dclk              620 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	clk_disable(vop->dclk);
dclk              691 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	clk_disable(vop->dclk);
dclk             1076 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999);
dclk             1193 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
dclk             1657 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
dclk             1658 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	if (IS_ERR(vop->dclk)) {
dclk             1660 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 		return PTR_ERR(vop->dclk);
dclk             1669 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	ret = clk_prepare(vop->dclk);
dclk             1749 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	clk_unprepare(vop->dclk);
dclk             1917 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	clk_unprepare(vop->dclk);
dclk               28 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk               30 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
dclk               36 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk               38 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
dclk               45 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk               48 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
dclk               56 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk               59 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
dclk               73 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk               74 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_tcon *tcon = dclk->tcon;
dclk              118 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk              121 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
dclk              127 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk              130 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
dclk              140 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk = hw_to_dclk(hw);
dclk              145 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
dclk              169 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	struct sun4i_dclk *dclk;
dclk              179 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
dclk              180 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	if (!dclk)
dclk              182 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	dclk->tcon = tcon;
dclk              190 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	dclk->regmap = tcon->regs;
dclk              191 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	dclk->hw.init = &init;
dclk              193 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	tcon->dclk = clk_register(dev, &dclk->hw);
dclk              194 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	if (IS_ERR(tcon->dclk))
dclk              195 drivers/gpu/drm/sun4i/sun4i_dotclock.c 		return PTR_ERR(tcon->dclk);
dclk              203 drivers/gpu/drm/sun4i/sun4i_dotclock.c 	clk_unregister(tcon->dclk);
dclk              121 drivers/gpu/drm/sun4i/sun4i_rgb.c 	rounded_rate = clk_round_rate(tcon->dclk, rate);
dclk               93 drivers/gpu/drm/sun4i/sun4i_tcon.c 		clk = tcon->dclk;
dclk              271 drivers/gpu/drm/sun4i/sun4i_tcon.c 	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
dclk              564 drivers/gpu/drm/sun4i/sun4i_tcon.c 		clk_set_phase(tcon->dclk, 240);
dclk              567 drivers/gpu/drm/sun4i/sun4i_tcon.c 		clk_set_phase(tcon->dclk, 0);
dclk              249 drivers/gpu/drm/sun4i/sun4i_tcon.h 	struct clk			*dclk;
dclk              521 drivers/mfd/si476x-cmd.c 				      enum si476x_dclk_config dclk,
dclk              528 drivers/mfd/si476x-cmd.c 		PIN_CFG_BYTE(dclk),
dclk               41 drivers/mfd/si476x-i2c.c 						core->pinmux.dclk,
dclk              807 drivers/mfd/si476x-i2c.c 	    core->pinmux.dclk == SI476X_DCLK_DAUDIO     &&
dclk               20 drivers/siox/siox-bus-gpio.c 	struct gpio_desc *dclk;
dclk               38 drivers/siox/siox-bus-gpio.c 	gpiod_set_value_cansleep(ddata->dclk, 0);
dclk               60 drivers/siox/siox-bus-gpio.c 			gpiod_set_value_cansleep(ddata->dclk, 1);
dclk               62 drivers/siox/siox-bus-gpio.c 			gpiod_set_value_cansleep(ddata->dclk, 0);
dclk              117 drivers/siox/siox-bus-gpio.c 	ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW);
dclk              118 drivers/siox/siox-bus-gpio.c 	if (IS_ERR(ddata->dclk)) {
dclk              119 drivers/siox/siox-bus-gpio.c 		ret = PTR_ERR(ddata->dclk);
dclk             1016 drivers/video/fbdev/core/fbmon.c 	u32 dclk;
dclk             1105 drivers/video/fbdev/core/fbmon.c static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres)
dclk             1109 drivers/video/fbdev/core/fbmon.c 	dclk /= 1000;
dclk             1112 drivers/video/fbdev/core/fbmon.c 	h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk);
dclk             1156 drivers/video/fbdev/core/fbmon.c 	timings->dclk = timings->htotal * timings->hfreq;
dclk             1167 drivers/video/fbdev/core/fbmon.c 	timings->dclk = timings->htotal * timings->hfreq;
dclk             1172 drivers/video/fbdev/core/fbmon.c 	timings->hblank = fb_get_hblank_by_dclk(timings->dclk,
dclk             1175 drivers/video/fbdev/core/fbmon.c 	timings->hfreq = timings->dclk/timings->htotal;
dclk             1267 drivers/video/fbdev/core/fbmon.c 		if (timings->dclk > dclkmax) {
dclk             1268 drivers/video/fbdev/core/fbmon.c 			timings->dclk = dclkmax;
dclk             1281 drivers/video/fbdev/core/fbmon.c 		timings->dclk = PICOS2KHZ(val) * 1000;
dclk             1292 drivers/video/fbdev/core/fbmon.c 	     timings->dclk < dclkmin || timings->dclk > dclkmax))) {
dclk             1295 drivers/video/fbdev/core/fbmon.c 		var->pixclock = KHZ2PICOS(timings->dclk/1000);
dclk              276 drivers/video/fbdev/riva/nv_driver.c 	unsigned long dclk = 0;
dclk              286 drivers/video/fbdev/riva/nv_driver.c 				dclk = 800000;
dclk              288 drivers/video/fbdev/riva/nv_driver.c 				dclk = 1000000;
dclk              294 drivers/video/fbdev/riva/nv_driver.c 			dclk = 1000000;
dclk              303 drivers/video/fbdev/riva/nv_driver.c 			dclk = 800000;
dclk              306 drivers/video/fbdev/riva/nv_driver.c 			dclk = 1000000;
dclk              311 drivers/video/fbdev/riva/nv_driver.c 	return dclk;
dclk              974 drivers/video/fbdev/savage/savagefb_driver.c 	int width, dclk, i, j; /*, refresh; */
dclk             1017 drivers/video/fbdev/savage/savagefb_driver.c 	dclk = timings.Clock;
dclk             1022 drivers/video/fbdev/savage/savagefb_driver.c 		if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
dclk             1029 drivers/video/fbdev/savage/savagefb_driver.c 		    ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
dclk             1036 drivers/video/fbdev/savage/savagefb_driver.c 		   ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
dclk             1081 drivers/video/fbdev/savage/savagefb_driver.c 	SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
dclk              302 drivers/video/fbdev/ssd1307fb.c 	u32 precharge, dclk, com_invdir, compins;
dclk              374 drivers/video/fbdev/ssd1307fb.c 	dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4;
dclk              375 drivers/video/fbdev/ssd1307fb.c 	ret = ssd1307fb_write_cmd(par->client, dclk);
dclk              121 include/linux/mfd/si476x-platform.h 	enum si476x_dclk_config  dclk;
dclk              278 sound/soc/intel/skylake/skl-ssp-clk.c static void unregister_src_clk(struct skl_clk_data *dclk)
dclk              280 sound/soc/intel/skylake/skl-ssp-clk.c 	while (dclk->avail_clk_cnt--)
dclk              281 sound/soc/intel/skylake/skl-ssp-clk.c 		clkdev_drop(dclk->clk[dclk->avail_clk_cnt]->lookup);
dclk               94 sound/soc/meson/axg-pdm.c 	struct clk *dclk;
dclk              188 sound/soc/meson/axg-pdm.c 				 clk_get_rate(priv->dclk) * 2);
dclk              253 sound/soc/meson/axg-pdm.c 	ret = clk_set_rate(priv->dclk, rate * os);
dclk              276 sound/soc/meson/axg-pdm.c 	ret = clk_prepare_enable(priv->dclk);
dclk              294 sound/soc/meson/axg-pdm.c 	clk_disable_unprepare(priv->dclk);
dclk              621 sound/soc/meson/axg-pdm.c 	priv->dclk = devm_clk_get(dev, "dclk");
dclk              622 sound/soc/meson/axg-pdm.c 	if (IS_ERR(priv->dclk)) {
dclk              623 sound/soc/meson/axg-pdm.c 		ret = PTR_ERR(priv->dclk);