DP_SEC_GSP7_ENABLE 355 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ DP_SEC_GSP7_ENABLE 436 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint8_t DP_SEC_GSP7_ENABLE; DP_SEC_GSP7_ENABLE 567 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t DP_SEC_GSP7_ENABLE; DP_SEC_GSP7_ENABLE 865 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c DP_SEC_GSP7_ENABLE, 0, DP_SEC_GSP7_ENABLE 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ DP_SEC_GSP7_ENABLE 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h type DP_SEC_GSP7_ENABLE;\ DP_SEC_GSP7_ENABLE 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c DP_SEC_GSP7_ENABLE, 1, DP_SEC_GSP7_ENABLE 337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0); DP_SEC_GSP7_ENABLE 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable);