dcfclk_per_state  212 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0);
dcfclk_per_state  214 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
dcfclk_per_state  215 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency)));
dcfclk_per_state  217 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
dcfclk_per_state  219 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
dcfclk_per_state  221 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0);
dcfclk_per_state  222 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
dcfclk_per_state  223 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency)));
dcfclk_per_state  225 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
dcfclk_per_state  227 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
dcfclk_per_state  252 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i];
dcfclk_per_state 1006 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->dcfclk = v->dcfclk_per_state[v->voltage_level];
dcfclk_per_state  562 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
dcfclk_per_state  563 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
dcfclk_per_state  582 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
dcfclk_per_state  583 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
dcfclk_per_state  584 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
dcfclk_per_state  602 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
dcfclk_per_state  603 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
dcfclk_per_state  604 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
dcfclk_per_state  605 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk = v->dcfclk_per_state[v->voltage_level];
dcfclk_per_state  837 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
dcfclk_per_state  838 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
dcfclk_per_state  839 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
dcfclk_per_state  840 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
dcfclk_per_state  841 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
dcfclk_per_state  842 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
dcfclk_per_state  106 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h 	float dcfclk_per_state[number_of_states_plus_one + 1];