dcfclk_bypass      58 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c 		bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007;
dcfclk_bypass      59 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c 		if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4)
dcfclk_bypass      60 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c 			bypass->dcfclk_bypass = 0;
dcfclk_bypass     207 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
dcfclk_bypass     208 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
dcfclk_bypass     209 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		regs_and_bypass->dcfclk_bypass = 0;
dcfclk_bypass     227 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
dcfclk_bypass      92 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 	uint32_t dcfclk_bypass;
dcfclk_bypass     135 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 	uint32_t dcfclk_bypass;