dcfclk           1006 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->dcfclk = v->dcfclk_per_state[v->voltage_level];
dcfclk           1226 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0);
dcfclk           1234 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
dcfclk           1235 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
dcfclk           1237 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
dcfclk           1239 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
dcfclk           1241 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0);
dcfclk           1242 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
dcfclk           1243 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
dcfclk           1245 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
dcfclk           1247 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 		v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
dcfclk           1293 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw;
dcfclk           1383 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 	v->stutter_burst_time = v->part_of_burst_that_fits_in_rob * (v->average_read_bandwidth_gbyte_per_second * 1000.0) / v->total_data_read_bandwidth / v->return_bw + (v->min_full_det_buffering_time * v->total_data_read_bandwidth - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0);
dcfclk            480 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input.clks_cfg.dcfclk_mhz = v->dcfclk;
dcfclk            564 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		v->dcfclk = v->dcfclkv_nom0p8;
dcfclk            585 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		v->dcfclk = v->dcfclkv_max0p9;
dcfclk            605 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	v->dcfclk = v->dcfclk_per_state[v->voltage_level];
dcfclk           1135 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
dcfclk            197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
dcfclk            224 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			regs_and_bypass->dcfclk,
dcfclk            213 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h 	float dcfclk;
dcfclk             84 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 	uint32_t dcfclk;