DP_SEC_GSP3_ENABLE  879 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
DP_SEC_GSP3_ENABLE  905 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			DP_SEC_GSP3_ENABLE, 0,
DP_SEC_GSP3_ENABLE  158 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
DP_SEC_GSP3_ENABLE  241 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
DP_SEC_GSP3_ENABLE  432 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint8_t DP_SEC_GSP3_ENABLE;
DP_SEC_GSP3_ENABLE  563 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_SEC_GSP3_ENABLE;
DP_SEC_GSP3_ENABLE  741 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
DP_SEC_GSP3_ENABLE  861 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		DP_SEC_GSP3_ENABLE, 0,
DP_SEC_GSP3_ENABLE  209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
DP_SEC_GSP3_ENABLE  393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	type DP_SEC_GSP3_ENABLE;\