DP_SEC_GSP2_ENABLE  878 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
DP_SEC_GSP2_ENABLE  904 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			DP_SEC_GSP2_ENABLE, 0,
DP_SEC_GSP2_ENABLE  157 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
DP_SEC_GSP2_ENABLE  240 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
DP_SEC_GSP2_ENABLE  431 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint8_t DP_SEC_GSP2_ENABLE;
DP_SEC_GSP2_ENABLE  562 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_SEC_GSP2_ENABLE;
DP_SEC_GSP2_ENABLE  740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
DP_SEC_GSP2_ENABLE  860 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		DP_SEC_GSP2_ENABLE, 0,
DP_SEC_GSP2_ENABLE  208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
DP_SEC_GSP2_ENABLE  392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	type DP_SEC_GSP2_ENABLE;\