DP_SEC_GSP0_ENABLE  877 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
DP_SEC_GSP0_ENABLE  902 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			DP_SEC_GSP0_ENABLE, 0,
DP_SEC_GSP0_ENABLE  154 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
DP_SEC_GSP0_ENABLE  237 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
DP_SEC_GSP0_ENABLE  428 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint8_t DP_SEC_GSP0_ENABLE;
DP_SEC_GSP0_ENABLE  559 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_SEC_GSP0_ENABLE;
DP_SEC_GSP0_ENABLE  739 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
DP_SEC_GSP0_ENABLE  858 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		DP_SEC_GSP0_ENABLE, 0,
DP_SEC_GSP0_ENABLE  205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
DP_SEC_GSP0_ENABLE  389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	type DP_SEC_GSP0_ENABLE;\