DP_SEC_CNTL2      770 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
DP_SEC_CNTL2      774 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
DP_SEC_CNTL2      777 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
DP_SEC_CNTL2      836 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
DP_SEC_CNTL2       84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_CNTL2, DP, id), \
DP_SEC_CNTL2      129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DP_SEC_CNTL2;
DP_SEC_CNTL2      226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1);
DP_SEC_CNTL2      338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0);