dce_mi 31 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.ctx dce_mi 33 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->regs->reg dce_mi 37 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->shifts->field_name, dce_mi->masks->field_name dce_mi 139 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); dce_mi 164 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 178 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 197 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 229 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 248 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 271 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); dce_mi 274 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_urgency_watermark(dce_mi, 2, /* set a */ dce_mi 276 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_urgency_watermark(dce_mi, 1, /* set d */ dce_mi 282 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */ dce_mi 283 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */ dce_mi 285 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */ dce_mi 286 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */ dce_mi 296 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); dce_mi 299 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_urgency_watermark(dce_mi, 0, /* set a */ dce_mi 301 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_urgency_watermark(dce_mi, 1, /* set b */ dce_mi 303 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_urgency_watermark(dce_mi, 2, /* set c */ dce_mi 305 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_urgency_watermark(dce_mi, 3, /* set d */ dce_mi 311 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */ dce_mi 312 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */ dce_mi 313 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */ dce_mi 314 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */ dce_mi 316 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark); /* set a */ dce_mi 317 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark); /* set b */ dce_mi 318 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark); /* set c */ dce_mi 319 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark); /* set d */ dce_mi 329 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); dce_mi 332 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_urgency_watermark(dce_mi, 0, /* set a */ dce_mi 334 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_urgency_watermark(dce_mi, 1, /* set b */ dce_mi 336 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_urgency_watermark(dce_mi, 2, /* set c */ dce_mi 338 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_urgency_watermark(dce_mi, 3, /* set d */ dce_mi 344 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */ dce_mi 345 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */ dce_mi 346 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */ dce_mi 347 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */ dce_mi 349 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark, stutter_entry.a_mark); /* set a */ dce_mi 350 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark, stutter_entry.b_mark); /* set b */ dce_mi 351 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark, stutter_entry.c_mark); /* set c */ dce_mi 352 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce120_program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark, stutter_entry.d_mark); /* set d */ dce_mi 356 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, const union dc_tiling_info *info) dce_mi 358 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ dce_mi 372 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ dce_mi 392 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 433 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 513 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); dce_mi 516 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_tiling(dce_mi, tiling_info); dce_mi 517 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_size_and_rotation(dce_mi, rotation, plane_size); dce_mi 521 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_grph_pixel_format(dce_mi, format); dce_mi 577 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); dce_mi 608 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (dce_mi->wa.single_head_rdreq_dmif_limit) { dce_mi 610 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->wa.single_head_rdreq_dmif_limit; dce_mi 621 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); dce_mi 638 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (dce_mi->wa.single_head_rdreq_dmif_limit) { dce_mi 640 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->wa.single_head_rdreq_dmif_limit; dce_mi 649 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 663 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 679 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input); dce_mi 695 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input); dce_mi 707 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_pri_addr(dce_mi, address->grph.addr); dce_mi 713 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_pri_addr(dce_mi, address->grph_stereo.left_addr); dce_mi 714 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_sec_addr(dce_mi, address->grph_stereo.right_addr); dce_mi 769 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 776 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.ctx = ctx; dce_mi 778 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.inst = inst; dce_mi 779 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.funcs = &dce_mi_funcs; dce_mi 781 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->regs = regs; dce_mi 782 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->shifts = mi_shift; dce_mi 783 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->masks = mi_mask; dce_mi 787 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 794 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask); dce_mi 795 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.funcs = &dce112_mi_funcs; dce_mi 799 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c struct dce_mem_input *dce_mi, dce_mi 806 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask); dce_mi 807 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.funcs = &dce120_mi_funcs; dce_mi 341 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h struct dce_mem_input *dce_mi, dce_mi 349 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h struct dce_mem_input *dce_mi, dce_mi 357 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h struct dce_mem_input *dce_mi, dce_mi 513 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), dce_mi 516 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (!dce_mi) { dce_mi 521 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); dce_mi 522 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce_mi->wa.single_head_rdreq_dmif_limit = 2; dce_mi 523 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &dce_mi->base; dce_mi 1035 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c struct dce_mem_input *dce_mi, dce_mi 1038 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dce_mi->base.funcs = &dce110_mem_input_v_funcs; dce_mi 1039 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dce_mi->base.ctx = ctx; dce_mi 32 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h struct dce_mem_input *dce_mi, dce_mi 559 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), dce_mi 562 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!dce_mi) { dce_mi 567 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); dce_mi 568 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce_mi->wa.single_head_rdreq_dmif_limit = 3; dce_mi 569 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &dce_mi->base; dce_mi 528 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), dce_mi 531 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!dce_mi) { dce_mi 536 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); dce_mi 537 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &dce_mi->base; dce_mi 797 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), dce_mi 800 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (!dce_mi) { dce_mi 805 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); dce_mi 806 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &dce_mi->base; dce_mi 625 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), dce_mi 628 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!dce_mi) { dce_mi 633 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); dce_mi 634 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce_mi->wa.single_head_rdreq_dmif_limit = 2; dce_mi 635 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &dce_mi->base;