DP_SEC_CNTL      1617 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
DP_SEC_CNTL      1618 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
DP_SEC_CNTL      1619 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
DP_SEC_CNTL      1620 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL        67 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
DP_SEC_CNTL       148 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DP_SEC_CNTL;
DP_SEC_CNTL       877 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
DP_SEC_CNTL       878 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
DP_SEC_CNTL       879 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
DP_SEC_CNTL       888 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	value = REG_READ(DP_SEC_CNTL);
DP_SEC_CNTL       890 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL       901 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_SET_7(DP_SEC_CNTL, 0,
DP_SEC_CNTL       914 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	value = REG_READ(DP_SEC_CNTL);
DP_SEC_CNTL       916 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL      1504 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
DP_SEC_CNTL      1507 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE_2(DP_SEC_CNTL,
DP_SEC_CNTL      1512 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL      1522 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE_5(DP_SEC_CNTL,
DP_SEC_CNTL      1531 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	value = REG_READ(DP_SEC_CNTL);
DP_SEC_CNTL      1533 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL        87 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
DP_SEC_CNTL       154 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
DP_SEC_CNTL       155 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
DP_SEC_CNTL       156 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
DP_SEC_CNTL       157 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
DP_SEC_CNTL       158 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
DP_SEC_CNTL       159 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
DP_SEC_CNTL       160 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
DP_SEC_CNTL       198 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
DP_SEC_CNTL       199 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
DP_SEC_CNTL       200 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
DP_SEC_CNTL       201 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
DP_SEC_CNTL       661 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_SEC_CNTL;
DP_SEC_CNTL        60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
DP_SEC_CNTL       102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	uint32_t DP_SEC_CNTL;
DP_SEC_CNTL       739 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
DP_SEC_CNTL       740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
DP_SEC_CNTL       741 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
DP_SEC_CNTL       751 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	value = REG_READ(DP_SEC_CNTL);
DP_SEC_CNTL       753 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL       845 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	value = REG_READ(DP_SEC_CNTL);
DP_SEC_CNTL       847 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL       857 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_SET_10(DP_SEC_CNTL, 0,
DP_SEC_CNTL       872 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	value = REG_READ(DP_SEC_CNTL);
DP_SEC_CNTL       874 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL      1443 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
DP_SEC_CNTL      1446 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE_2(DP_SEC_CNTL,
DP_SEC_CNTL      1451 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL      1461 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE_5(DP_SEC_CNTL,
DP_SEC_CNTL      1471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	value = REG_READ(DP_SEC_CNTL);
DP_SEC_CNTL      1473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
DP_SEC_CNTL        83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
DP_SEC_CNTL       128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DP_SEC_CNTL;
DP_SEC_CNTL       332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE_2(DP_SEC_CNTL,
DP_SEC_CNTL       337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0);
DP_SEC_CNTL       359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable);
DP_SEC_CNTL       360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
DP_SEC_CNTL       436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);