DP_SEC_ASP_ENABLE 1617 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
DP_SEC_ASP_ENABLE 1504 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
DP_SEC_ASP_ENABLE 1523 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			DP_SEC_ASP_ENABLE, 0,
DP_SEC_ASP_ENABLE  198 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
DP_SEC_ASP_ENABLE  278 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
DP_SEC_ASP_ENABLE  474 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint8_t DP_SEC_ASP_ENABLE;
DP_SEC_ASP_ENABLE  605 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_SEC_ASP_ENABLE;
DP_SEC_ASP_ENABLE 1443 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
DP_SEC_ASP_ENABLE 1462 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 			DP_SEC_ASP_ENABLE, 0,
DP_SEC_ASP_ENABLE  250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
DP_SEC_ASP_ENABLE  440 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	type DP_SEC_ASP_ENABLE;\