dccg_dcn           36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	(dccg_dcn->regs->reg)
dccg_dcn           40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
dccg_dcn           43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	dccg_dcn->base.ctx
dccg_dcn           52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
dccg_dcn          102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
dccg_dcn          122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
dccg_dcn          125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) {
dccg_dcn          162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
dccg_dcn          165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	if (dccg_dcn == NULL) {
dccg_dcn          170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	base = &dccg_dcn->base;
dccg_dcn          174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	dccg_dcn->regs = regs;
dccg_dcn          175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	dccg_dcn->dccg_shift = dccg_shift;
dccg_dcn          176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	dccg_dcn->dccg_mask = dccg_mask;
dccg_dcn          178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	return &dccg_dcn->base;
dccg_dcn          183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg);
dccg_dcn          185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	kfree(dccg_dcn);