dcc_en 514 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t dcc_en = enable ? 1 : 0; dcc_en 519 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PRIMARY_SURFACE_DCC_EN, dcc_en, dcc_en 521 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c SECONDARY_SURFACE_DCC_EN, dcc_en, dcc_en 1002 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PRIMARY_SURFACE_DCC_EN, &s->dcc_en); dcc_en 643 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t dcc_en; dcc_en 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c s->dcc_en, dcc_en 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c s->dcc_en, dcc_en 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c s->dcc_en, dcc_en 402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t dcc_en = enable ? 1 : 0; dcc_en 407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PRIMARY_SURFACE_DCC_EN, dcc_en, dcc_en 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c SECONDARY_SURFACE_DCC_EN, dcc_en, dcc_en 1200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PRIMARY_SURFACE_DCC_EN, &s->dcc_en); dcc_en 1011 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c bool dcc_en; dcc_en 1182 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c dcc_en = e2e_pipe_param.pipe.src.dcc; dcc_en 1342 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (dcc_en && vm_en) dcc_en 1344 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (dcc_en) dcc_en 1396 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (vm_en && dcc_en) { dcc_en 1410 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c if (vm_en || dcc_en) {