DP_MSA_TIMING_PARAM1  399 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (REG(DP_MSA_TIMING_PARAM1)) {
DP_MSA_TIMING_PARAM1  467 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		if (REG(DP_MSA_TIMING_PARAM1))
DP_MSA_TIMING_PARAM1  468 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
DP_MSA_TIMING_PARAM1  109 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
DP_MSA_TIMING_PARAM1  690 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DP_MSA_TIMING_PARAM1;
DP_MSA_TIMING_PARAM1  430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
DP_MSA_TIMING_PARAM1   76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
DP_MSA_TIMING_PARAM1  161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DP_MSA_TIMING_PARAM1;