dcache 300 arch/arc/include/asm/arcregs.h struct cpuinfo_arc_cache icache, dcache, slc; dcache 55 arch/arc/mm/cache.c PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); dcache 173 arch/arc/mm/cache.c p_dc = &cpuinfo_arc700[cpu].dcache; dcache 1241 arch/arc/mm/cache.c struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; dcache 238 arch/mips/include/asm/cpu-features.h #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) dcache 244 arch/mips/include/asm/cpu-features.h #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) dcache 485 arch/mips/include/asm/cpu-features.h #define cpu_dcache_line_size() cpu_data[0].dcache.linesz dcache 76 arch/mips/include/asm/cpu-info.h struct cache_desc dcache; /* Primary D or combined I/D cache */ dcache 70 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h # Flush dcache after config change dcache 571 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) dcache 574 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) dcache 578 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) dcache 581 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) dcache 585 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) dcache 586 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) dcache 604 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, dcache 607 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, dcache 610 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, dcache 633 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) dcache 664 arch/mips/include/asm/r4kcache.h __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) dcache 671 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) dcache 675 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) dcache 30 arch/mips/kernel/cacheinfo.c if (c->dcache.waysize) dcache 81 arch/mips/kernel/cacheinfo.c populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA); dcache 85 arch/mips/kernel/cacheinfo.c populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED); dcache 244 arch/mips/kernel/pm-cps.c unsigned line_size = cpu_info->dcache.linesz; dcache 472 arch/mips/kernel/pm-cps.c cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache, dcache 639 arch/mips/kernel/traps.c regs->regs[rt] = min(current_cpu_data.dcache.linesz, dcache 2533 arch/mips/kvm/emulate.c arch->gprs[rt] = min(current_cpu_data.dcache.linesz, dcache 481 arch/mips/loongson64/loongson-3/smp.c [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); dcache 563 arch/mips/loongson64/loongson-3/smp.c [sets] "r" (cpu_data[smp_processor_id()].dcache.sets), dcache 626 arch/mips/loongson64/loongson-3/smp.c [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); dcache 187 arch/mips/mm/c-octeon.c c->dcache.linesz = 128; dcache 189 arch/mips/mm/c-octeon.c c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ dcache 191 arch/mips/mm/c-octeon.c c->dcache.sets = 1; /* CN3XXX has one Dcache set */ dcache 192 arch/mips/mm/c-octeon.c c->dcache.ways = 64; dcache 194 arch/mips/mm/c-octeon.c c->dcache.sets * c->dcache.ways * c->dcache.linesz; dcache 195 arch/mips/mm/c-octeon.c c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; dcache 206 arch/mips/mm/c-octeon.c c->dcache.linesz = 128; dcache 207 arch/mips/mm/c-octeon.c c->dcache.ways = 32; dcache 208 arch/mips/mm/c-octeon.c c->dcache.sets = 8; dcache 209 arch/mips/mm/c-octeon.c dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; dcache 220 arch/mips/mm/c-octeon.c c->dcache.linesz = 128; dcache 221 arch/mips/mm/c-octeon.c c->dcache.ways = 32; dcache 222 arch/mips/mm/c-octeon.c c->dcache.sets = 8; dcache 223 arch/mips/mm/c-octeon.c dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; dcache 234 arch/mips/mm/c-octeon.c c->dcache.waysize = dcache_size / c->dcache.ways; dcache 237 arch/mips/mm/c-octeon.c c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); dcache 249 arch/mips/mm/c-octeon.c dcache_size >> 10, c->dcache.ways, dcache 250 arch/mips/mm/c-octeon.c c->dcache.sets, c->dcache.linesz); dcache 1094 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1095 arch/mips/mm/c-r4k.c c->dcache.ways = 2; dcache 1096 arch/mips/mm/c-r4k.c c->dcache.waybit= __ffs(dcache_size/2); dcache 1108 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1109 arch/mips/mm/c-r4k.c c->dcache.ways = 2; dcache 1110 arch/mips/mm/c-r4k.c c->dcache.waybit = 0; dcache 1122 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1123 arch/mips/mm/c-r4k.c c->dcache.ways = 4; dcache 1124 arch/mips/mm/c-r4k.c c->dcache.waybit = 0; dcache 1142 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1143 arch/mips/mm/c-r4k.c c->dcache.ways = 1; dcache 1144 arch/mips/mm/c-r4k.c c->dcache.waybit = 0; /* does not matter */ dcache 1159 arch/mips/mm/c-r4k.c c->dcache.linesz = 32; dcache 1160 arch/mips/mm/c-r4k.c c->dcache.ways = 2; dcache 1161 arch/mips/mm/c-r4k.c c->dcache.waybit = 0; dcache 1186 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1187 arch/mips/mm/c-r4k.c c->dcache.ways = 2; dcache 1188 arch/mips/mm/c-r4k.c c->dcache.waybit = __ffs(dcache_size/2); dcache 1203 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1204 arch/mips/mm/c-r4k.c c->dcache.ways = 1; dcache 1205 arch/mips/mm/c-r4k.c c->dcache.waybit = 0; /* does not matter */ dcache 1219 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1220 arch/mips/mm/c-r4k.c c->dcache.ways = 4; dcache 1221 arch/mips/mm/c-r4k.c c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); dcache 1237 arch/mips/mm/c-r4k.c c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); dcache 1239 arch/mips/mm/c-r4k.c c->dcache.ways = 4; dcache 1241 arch/mips/mm/c-r4k.c c->dcache.ways = 2; dcache 1242 arch/mips/mm/c-r4k.c c->dcache.waybit = 0; dcache 1261 arch/mips/mm/c-r4k.c c->dcache.linesz = 2 << lsize; dcache 1263 arch/mips/mm/c-r4k.c c->dcache.linesz = 0; dcache 1264 arch/mips/mm/c-r4k.c c->dcache.sets = 64 << ((config1 >> 13) & 7); dcache 1265 arch/mips/mm/c-r4k.c c->dcache.ways = 1 + ((config1 >> 7) & 7); dcache 1266 arch/mips/mm/c-r4k.c dcache_size = c->dcache.sets * dcache 1267 arch/mips/mm/c-r4k.c c->dcache.ways * dcache 1268 arch/mips/mm/c-r4k.c c->dcache.linesz; dcache 1269 arch/mips/mm/c-r4k.c c->dcache.waybit = 0; dcache 1282 arch/mips/mm/c-r4k.c c->dcache.linesz = 128; dcache 1283 arch/mips/mm/c-r4k.c c->dcache.ways = 8; dcache 1284 arch/mips/mm/c-r4k.c c->dcache.sets = 8; dcache 1285 arch/mips/mm/c-r4k.c dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; dcache 1321 arch/mips/mm/c-r4k.c c->dcache.flags = 0; dcache 1329 arch/mips/mm/c-r4k.c c->dcache.linesz = lsize ? 2 << lsize : 0; dcache 1331 arch/mips/mm/c-r4k.c c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); dcache 1332 arch/mips/mm/c-r4k.c c->dcache.ways = 1 + ((config1 >> 7) & 7); dcache 1334 arch/mips/mm/c-r4k.c dcache_size = c->dcache.sets * dcache 1335 arch/mips/mm/c-r4k.c c->dcache.ways * dcache 1336 arch/mips/mm/c-r4k.c c->dcache.linesz; dcache 1337 arch/mips/mm/c-r4k.c c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); dcache 1359 arch/mips/mm/c-r4k.c c->dcache.waysize = dcache_size / c->dcache.ways; dcache 1363 arch/mips/mm/c-r4k.c c->dcache.sets = c->dcache.linesz ? dcache 1364 arch/mips/mm/c-r4k.c dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; dcache 1380 arch/mips/mm/c-r4k.c c->dcache.flags |= MIPS_CACHE_PINDEX; dcache 1413 arch/mips/mm/c-r4k.c c->dcache.flags |= MIPS_CACHE_PINDEX; dcache 1418 arch/mips/mm/c-r4k.c if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) dcache 1419 arch/mips/mm/c-r4k.c c->dcache.flags |= MIPS_CACHE_ALIASES; dcache 1423 arch/mips/mm/c-r4k.c if (c->dcache.flags & MIPS_CACHE_PINDEX) dcache 1424 arch/mips/mm/c-r4k.c c->dcache.flags &= ~MIPS_CACHE_ALIASES; dcache 1452 arch/mips/mm/c-r4k.c c->dcache.flags &= ~MIPS_CACHE_ALIASES; dcache 1469 arch/mips/mm/c-r4k.c dcache_size >> 10, way_string[c->dcache.ways], dcache 1470 arch/mips/mm/c-r4k.c (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", dcache 1471 arch/mips/mm/c-r4k.c (c->dcache.flags & MIPS_CACHE_ALIASES) ? dcache 1473 arch/mips/mm/c-r4k.c c->dcache.linesz); dcache 1848 arch/mips/mm/c-r4k.c if (c->dcache.linesz && cpu_has_dc_aliases) dcache 1850 arch/mips/mm/c-r4k.c c->dcache.sets * c->dcache.linesz - 1, dcache 308 arch/mips/mm/c-tx39.c current_cpu_data.dcache.ways = 1; dcache 309 arch/mips/mm/c-tx39.c current_cpu_data.dcache.linesz = 4; dcache 314 arch/mips/mm/c-tx39.c current_cpu_data.dcache.ways = 2; dcache 315 arch/mips/mm/c-tx39.c current_cpu_data.dcache.linesz = 16; dcache 321 arch/mips/mm/c-tx39.c current_cpu_data.dcache.ways = 1; dcache 322 arch/mips/mm/c-tx39.c current_cpu_data.dcache.linesz = 16; dcache 388 arch/mips/mm/c-tx39.c (dcache_size / current_cpu_data.dcache.ways) - 1, dcache 398 arch/mips/mm/c-tx39.c current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways; dcache 402 arch/mips/mm/c-tx39.c current_cpu_data.dcache.sets = dcache 403 arch/mips/mm/c-tx39.c current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz; dcache 405 arch/mips/mm/c-tx39.c if (current_cpu_data.dcache.waysize > PAGE_SIZE) dcache 406 arch/mips/mm/c-tx39.c current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES; dcache 409 arch/mips/mm/c-tx39.c current_cpu_data.dcache.waybit = 0; dcache 414 arch/mips/mm/c-tx39.c dcache_size >> 10, current_cpu_data.dcache.linesz); dcache 363 arch/powerpc/kernel/cacheinfo.c struct cache *dcache, *icache; dcache 368 arch/powerpc/kernel/cacheinfo.c dcache = new_cache(CACHE_TYPE_DATA, level, node); dcache 371 arch/powerpc/kernel/cacheinfo.c if (!dcache || !icache) dcache 374 arch/powerpc/kernel/cacheinfo.c dcache->next_local = icache; dcache 376 arch/powerpc/kernel/cacheinfo.c return dcache; dcache 378 arch/powerpc/kernel/cacheinfo.c release_cache(dcache); dcache 133 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); dcache 134 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); dcache 136 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); dcache 137 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); dcache 163 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN); dcache 164 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); dcache 165 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); dcache 166 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); dcache 64 arch/sh/include/asm/cacheflush.h if (boot_cpu_data.dcache.n_aliases && PageAnon(page)) dcache 83 arch/sh/include/asm/processor.h struct cache_info dcache; /* Primary D-cache */ dcache 128 arch/sh/kernel/cpu/init.c waysize = current_cpu_data.dcache.sets; dcache 139 arch/sh/kernel/cpu/init.c waysize <<= current_cpu_data.dcache.entry_shift; dcache 147 arch/sh/kernel/cpu/init.c ways = current_cpu_data.dcache.ways; dcache 155 arch/sh/kernel/cpu/init.c addr += current_cpu_data.dcache.linesz) dcache 158 arch/sh/kernel/cpu/init.c addrstart += current_cpu_data.dcache.way_incr; dcache 170 arch/sh/kernel/cpu/init.c if (current_cpu_data.dcache.ways > 1) dcache 204 arch/sh/kernel/cpu/init.c l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); dcache 206 arch/sh/kernel/cpu/init.c if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) dcache 313 arch/sh/kernel/cpu/init.c current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - dcache 314 arch/sh/kernel/cpu/init.c current_cpu_data.dcache.linesz; dcache 316 arch/sh/kernel/cpu/init.c current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * dcache 317 arch/sh/kernel/cpu/init.c current_cpu_data.dcache.linesz; dcache 325 arch/sh/kernel/cpu/init.c current_cpu_data.dcache.way_size - 1, dcache 118 arch/sh/kernel/cpu/proc.c show_cacheinfo(m, "dcache", c->dcache); dcache 34 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.ways = 4; dcache 35 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.way_incr = (1<<12); dcache 36 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.sets = 256; dcache 37 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.entry_shift = 4; dcache 38 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; dcache 39 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.flags = 0; dcache 56 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.ways = 1; dcache 57 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.sets = 256; dcache 58 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.entry_shift = 5; dcache 59 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.linesz = 32; dcache 60 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.flags = 0; dcache 67 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; dcache 69 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.icache = boot_cpu_data.dcache; dcache 43 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.dcache.ways = 4; dcache 44 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.dcache.way_incr = (1 << 11); dcache 45 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.dcache.sets = 128; dcache 46 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.dcache.entry_shift = 4; dcache 47 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; dcache 48 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.dcache.flags = 0; dcache 56 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.icache = boot_cpu_data.dcache; dcache 50 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.ways = 4; dcache 51 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.entry_shift = 4; dcache 52 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; dcache 53 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.flags = 0; dcache 60 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.way_incr = (1 << 11); dcache 61 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.entry_mask = 0x7f0; dcache 62 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.sets = 128; dcache 67 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.way_incr = (1 << 12); dcache 68 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.entry_mask = 0xff0; dcache 69 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.sets = 256; dcache 91 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.way_incr = (1 << 13); dcache 92 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.entry_mask = 0x1ff0; dcache 93 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.sets = 512; dcache 104 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; dcache 105 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.icache = boot_cpu_data.dcache; dcache 44 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.way_incr = (1 << 14); dcache 45 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.entry_shift = 5; dcache 46 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.sets = 512; dcache 47 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.ways = 1; dcache 48 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; dcache 68 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.ways = 4; dcache 172 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.ways = 2; dcache 177 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.ways = 2; dcache 193 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.ways = 2; dcache 210 arch/sh/kernel/cpu/sh4/probe.c if (boot_cpu_data.dcache.ways > 1) { dcache 212 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.way_incr = (size >> 1); dcache 213 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.dcache.sets = (size >> 6); dcache 59 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.dcache = boot_cpu_data.icache; dcache 65 arch/sh/kernel/cpu/sh5/probe.c set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags)); dcache 67 arch/sh/kernel/cpu/sh5/probe.c set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags)); dcache 49 arch/sh/mm/cache-debugfs.c cache = ¤t_cpu_data.dcache; dcache 60 arch/sh/mm/cache-sh2a.c nr_ways = current_cpu_data.dcache.ways; dcache 68 arch/sh/mm/cache-sh2a.c end = begin + (nr_ways * current_cpu_data.dcache.way_size); dcache 107 arch/sh/mm/cache-sh2a.c int nr_ways = current_cpu_data.dcache.ways; dcache 46 arch/sh/mm/cache-sh3.c for (j = 0; j < current_cpu_data.dcache.ways; j++) { dcache 50 arch/sh/mm/cache-sh3.c addr = addrstart | (v & current_cpu_data.dcache.entry_mask); dcache 62 arch/sh/mm/cache-sh3.c addrstart += current_cpu_data.dcache.way_incr; dcache 87 arch/sh/mm/cache-sh3.c (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC; dcache 154 arch/sh/mm/cache-sh4.c (current_cpu_data.dcache.sets << dcache 155 arch/sh/mm/cache-sh4.c current_cpu_data.dcache.entry_shift) * dcache 156 arch/sh/mm/cache-sh4.c current_cpu_data.dcache.ways; dcache 158 arch/sh/mm/cache-sh4.c entry_offset = 1 << current_cpu_data.dcache.entry_shift; dcache 242 arch/sh/mm/cache-sh4.c map_coherent = (current_cpu_data.dcache.n_aliases && dcache 293 arch/sh/mm/cache-sh4.c if (boot_cpu_data.dcache.n_aliases == 0) dcache 321 arch/sh/mm/cache-sh4.c struct cache_info *dcache; dcache 326 arch/sh/mm/cache-sh4.c dcache = &boot_cpu_data.dcache; dcache 328 arch/sh/mm/cache-sh4.c way_count = dcache->ways; dcache 329 arch/sh/mm/cache-sh4.c way_incr = dcache->way_incr; dcache 249 arch/sh/mm/cache-sh5.c cpu_data->dcache.entry_mask) >> dcache 250 arch/sh/mm/cache-sh5.c cpu_data->dcache.entry_shift; dcache 254 arch/sh/mm/cache-sh5.c set_offset &= (cpu_data->dcache.sets - 1); dcache 256 arch/sh/mm/cache-sh5.c (set_offset << cpu_data->dcache.entry_shift); dcache 265 arch/sh/mm/cache-sh5.c eaddr1 = eaddr0 + cpu_data->dcache.way_size * dcache 266 arch/sh/mm/cache-sh5.c cpu_data->dcache.ways; dcache 269 arch/sh/mm/cache-sh5.c eaddr += cpu_data->dcache.way_size) { dcache 274 arch/sh/mm/cache-sh5.c eaddr1 = eaddr0 + cpu_data->dcache.way_size * dcache 275 arch/sh/mm/cache-sh5.c cpu_data->dcache.ways; dcache 278 arch/sh/mm/cache-sh5.c eaddr += cpu_data->dcache.way_size) { dcache 283 arch/sh/mm/cache-sh5.c if (test_bit(SH_CACHE_MODE_WT, &(cpu_data->dcache.flags))) dcache 306 arch/sh/mm/cache-sh5.c sh64_dcache_purge_sets(0, cpu_data->dcache.sets); dcache 36 arch/sh/mm/cache-sh7705.c ways = current_cpu_data.dcache.ways; dcache 37 arch/sh/mm/cache-sh7705.c waysize = current_cpu_data.dcache.sets; dcache 38 arch/sh/mm/cache-sh7705.c waysize <<= current_cpu_data.dcache.entry_shift; dcache 47 arch/sh/mm/cache-sh7705.c addr += current_cpu_data.dcache.linesz) { dcache 58 arch/sh/mm/cache-sh7705.c addrstart += current_cpu_data.dcache.way_incr; dcache 104 arch/sh/mm/cache-sh7705.c ways = current_cpu_data.dcache.ways; dcache 105 arch/sh/mm/cache-sh7705.c waysize = current_cpu_data.dcache.sets; dcache 106 arch/sh/mm/cache-sh7705.c waysize <<= current_cpu_data.dcache.entry_shift; dcache 115 arch/sh/mm/cache-sh7705.c addr += current_cpu_data.dcache.linesz) { dcache 125 arch/sh/mm/cache-sh7705.c addrstart += current_cpu_data.dcache.way_incr; dcache 27 arch/sh/mm/cache-shx3.c if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) { dcache 31 arch/sh/mm/cache-shx3.c boot_cpu_data.dcache.n_aliases = 0; dcache 64 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && dcache 71 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases) dcache 83 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && dcache 90 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases) dcache 102 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) && dcache 142 arch/sh/mm/cache.c if (!boot_cpu_data.dcache.n_aliases) dcache 158 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && dcache 179 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases == 0) dcache 187 arch/sh/mm/cache.c if (boot_cpu_data.dcache.n_aliases == 0) dcache 268 arch/sh/mm/cache.c boot_cpu_data.dcache.ways, dcache 269 arch/sh/mm/cache.c boot_cpu_data.dcache.sets, dcache 270 arch/sh/mm/cache.c boot_cpu_data.dcache.way_incr); dcache 272 arch/sh/mm/cache.c boot_cpu_data.dcache.entry_mask, dcache 273 arch/sh/mm/cache.c boot_cpu_data.dcache.alias_mask, dcache 274 arch/sh/mm/cache.c boot_cpu_data.dcache.n_aliases); dcache 300 arch/sh/mm/cache.c compute_alias(&boot_cpu_data.dcache); dcache 336 arch/sh/mm/cache.c (boot_cpu_data.dcache.sets == 512)) { dcache 65 drivers/gpio/gpio-aspeed.c u32 *dcache; dcache 356 drivers/gpio/gpio-aspeed.c gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); dcache 398 drivers/gpio/gpio-aspeed.c reg = gpio->dcache[GPIO_BANK(offset)]; dcache 404 drivers/gpio/gpio-aspeed.c gpio->dcache[GPIO_BANK(offset)] = reg; dcache 1187 drivers/gpio/gpio-aspeed.c gpio->dcache = devm_kcalloc(&pdev->dev, dcache 1189 drivers/gpio/gpio-aspeed.c if (!gpio->dcache) dcache 1199 drivers/gpio/gpio-aspeed.c gpio->dcache[i] = ioread32(addr); dcache 732 drivers/perf/qcom_l2_pmu.c L2CACHE_EVENT_ATTR(dcache-ops, L2_EVENT_DCACHE_OPS), dcache 227 drivers/soc/bcm/brcmstb/pm/pm-mips.c brcm_pm_do_s3(ctrl.aon_ctrl_base, current_cpu_data.dcache.linesz); dcache 72 fs/affs/amigaffs.h __be32 dcache;