dc_hpd_int_cntl  2855 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	u32 dc_hpd_int_cntl;
dc_hpd_int_cntl  2864 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
dc_hpd_int_cntl  2865 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
dc_hpd_int_cntl  2866 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
dc_hpd_int_cntl  2869 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
dc_hpd_int_cntl  2870 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		dc_hpd_int_cntl |= DC_HPDx_INT_EN;
dc_hpd_int_cntl  2871 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
dc_hpd_int_cntl  2947 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	u32 dc_hpd_int_cntl;
dc_hpd_int_cntl  2956 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
dc_hpd_int_cntl  2957 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
dc_hpd_int_cntl  2958 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
dc_hpd_int_cntl  2961 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
dc_hpd_int_cntl  2962 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
dc_hpd_int_cntl  2963 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);