DP_DSC_CNTL       167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DP_DSC_CNTL;
DP_DSC_CNTL       283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE_2(DP_DSC_CNTL,
DP_DSC_CNTL       351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
DP_DSC_CNTL       353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
DP_DSC_CNTL        37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(DP_DSC_CNTL, DP, id), \