dc_dsc_cfg 403 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dc_dsc_cfg 404 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dc_dsc_cfg 405 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; dc_dsc_cfg 415 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; dc_dsc_cfg 504 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dc_dsc_cfg 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); dc_dsc_cfg 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); dc_dsc_cfg 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c config->dc_dsc_cfg.bits_per_pixel, dc_dsc_cfg 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c config->dc_dsc_cfg.bits_per_pixel / 16, dc_dsc_cfg 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); dc_dsc_cfg 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); dc_dsc_cfg 314 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); dc_dsc_cfg 315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); dc_dsc_cfg 318 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && dc_dsc_cfg 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || dc_dsc_cfg 320 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c (dsc_cfg->dc_dsc_cfg.version_minor == 2 && dc_dsc_cfg 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || dc_dsc_cfg 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); dc_dsc_cfg 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 dc_dsc_cfg 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || dc_dsc_cfg 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || dc_dsc_cfg 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: dc_dsc_cfg 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || dc_dsc_cfg 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: dc_dsc_cfg 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || dc_dsc_cfg 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || dc_dsc_cfg 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { dc_dsc_cfg 341 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); dc_dsc_cfg 342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; dc_dsc_cfg 343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; dc_dsc_cfg 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; dc_dsc_cfg 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; dc_dsc_cfg 349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; dc_dsc_cfg 354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; dc_dsc_cfg 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; dc_dsc_cfg 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); dc_dsc_cfg 358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { dc_dsc_cfg 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); dc_dsc_cfg 363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; dc_dsc_cfg 2278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dc_dsc_cfg 2279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; dc_dsc_cfg 39 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h struct dc_dsc_config dc_dsc_cfg;