dc_clks           252 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		struct dm_pp_clock_levels *dc_clks,
dc_clks           263 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
dc_clks           265 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		dc_clks->num_levels = pp_clks->count;
dc_clks           270 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	for (i = 0; i < dc_clks->num_levels; i++) {
dc_clks           272 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
dc_clks           334 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		struct dm_pp_clock_levels *dc_clks)
dc_clks           346 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			get_default_clock_levels(clk_type, dc_clks);
dc_clks           353 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			get_default_clock_levels(clk_type, dc_clks);
dc_clks           358 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
dc_clks           392 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		for (i = 0; i < dc_clks->num_levels; i++) {
dc_clks           393 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
dc_clks           398 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 						dc_clks->num_levels, i);
dc_clks           399 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				dc_clks->num_levels = i > 0 ? i : 1;
dc_clks           404 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		for (i = 0; i < dc_clks->num_levels; i++) {
dc_clks           405 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
dc_clks           407 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 						dc_clks->num_levels, i);
dc_clks           408 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				dc_clks->num_levels = i > 0 ? i : 1;