DP_DPHY_TRAINING_PATTERN_SEL  244 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
DP_DPHY_TRAINING_PATTERN_SEL  560 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
DP_DPHY_TRAINING_PATTERN_SEL   60 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
DP_DPHY_TRAINING_PATTERN_SEL  141 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
DP_DPHY_TRAINING_PATTERN_SEL  216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
DP_DPHY_TRAINING_PATTERN_SEL  548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
DP_DPHY_TRAINING_PATTERN_SEL   53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
DP_DPHY_TRAINING_PATTERN_SEL   95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	uint32_t DP_DPHY_TRAINING_PATTERN_SEL;