DP_DPHY_HBR2_PATTERN_CONTROL 410 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) DP_DPHY_HBR2_PATTERN_CONTROL 411 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL 412 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); DP_DPHY_HBR2_PATTERN_CONTROL 92 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ DP_DPHY_HBR2_PATTERN_CONTROL 98 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ DP_DPHY_HBR2_PATTERN_CONTROL 105 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) DP_DPHY_HBR2_PATTERN_CONTROL 152 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; DP_DPHY_HBR2_PATTERN_CONTROL 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) DP_DPHY_HBR2_PATTERN_CONTROL 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); DP_DPHY_HBR2_PATTERN_CONTROL 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) DP_DPHY_HBR2_PATTERN_CONTROL 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; DP_DPHY_HBR2_PATTERN_CONTROL 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ DP_DPHY_HBR2_PATTERN_CONTROL 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h type DP_DPHY_HBR2_PATTERN_CONTROL;\