DP_DPHY_CNTL      143 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
DP_DPHY_CNTL      154 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	REG_UPDATE_4(DP_DPHY_CNTL,
DP_DPHY_CNTL       54 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_CNTL, DP, id), \
DP_DPHY_CNTL      134 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DP_DPHY_CNTL;
DP_DPHY_CNTL      115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
DP_DPHY_CNTL      126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	REG_UPDATE_4(DP_DPHY_CNTL,
DP_DPHY_CNTL       47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_CNTL, DP, id), \
DP_DPHY_CNTL       88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	uint32_t DP_DPHY_CNTL;
DP_DPHY_CNTL      175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
DP_DPHY_CNTL      182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);
DP_DPHY_CNTL      190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
DP_DPHY_CNTL      203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
DP_DPHY_CNTL      204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
DP_DPHY_CNTL      205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);