DP_DPHY_BS_SR_SWAP_CNTL  534 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
DP_DPHY_BS_SR_SWAP_CNTL   74 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
DP_DPHY_BS_SR_SWAP_CNTL   84 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
DP_DPHY_BS_SR_SWAP_CNTL   90 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
DP_DPHY_BS_SR_SWAP_CNTL   97 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
DP_DPHY_BS_SR_SWAP_CNTL  103 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
DP_DPHY_BS_SR_SWAP_CNTL  151 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
DP_DPHY_BS_SR_SWAP_CNTL  522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
DP_DPHY_BS_SR_SWAP_CNTL   64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
DP_DPHY_BS_SR_SWAP_CNTL  105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	uint32_t DP_DPHY_BS_SR_SWAP_CNTL;