dbi 102 drivers/gpu/drm/drm_mipi_dbi.c static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd) dbi 106 drivers/gpu/drm/drm_mipi_dbi.c if (!dbi->read_commands) dbi 110 drivers/gpu/drm/drm_mipi_dbi.c if (!dbi->read_commands[i]) dbi 112 drivers/gpu/drm/drm_mipi_dbi.c if (cmd == dbi->read_commands[i]) dbi 130 drivers/gpu/drm/drm_mipi_dbi.c int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val) dbi 132 drivers/gpu/drm/drm_mipi_dbi.c if (!dbi->read_commands) dbi 135 drivers/gpu/drm/drm_mipi_dbi.c if (!mipi_dbi_command_is_read(dbi, cmd)) dbi 138 drivers/gpu/drm/drm_mipi_dbi.c return mipi_dbi_command_buf(dbi, cmd, val, 1); dbi 152 drivers/gpu/drm/drm_mipi_dbi.c int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) dbi 162 drivers/gpu/drm/drm_mipi_dbi.c mutex_lock(&dbi->cmdlock); dbi 163 drivers/gpu/drm/drm_mipi_dbi.c ret = dbi->command(dbi, cmdbuf, data, len); dbi 164 drivers/gpu/drm/drm_mipi_dbi.c mutex_unlock(&dbi->cmdlock); dbi 173 drivers/gpu/drm/drm_mipi_dbi.c int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len) dbi 182 drivers/gpu/drm/drm_mipi_dbi.c ret = mipi_dbi_command_buf(dbi, cmd, buf, len); dbi 248 drivers/gpu/drm/drm_mipi_dbi.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 249 drivers/gpu/drm/drm_mipi_dbi.c bool swap = dbi->swap_bytes; dbi 264 drivers/gpu/drm/drm_mipi_dbi.c if (!dbi->dc || !full || swap || dbi 274 drivers/gpu/drm/drm_mipi_dbi.c mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, dbi 277 drivers/gpu/drm/drm_mipi_dbi.c mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, dbi 281 drivers/gpu/drm/drm_mipi_dbi.c ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, dbi 360 drivers/gpu/drm/drm_mipi_dbi.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 369 drivers/gpu/drm/drm_mipi_dbi.c mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0, dbi 371 drivers/gpu/drm/drm_mipi_dbi.c mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0, dbi 373 drivers/gpu/drm/drm_mipi_dbi.c mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, dbi 509 drivers/gpu/drm/drm_mipi_dbi.c if (!dbidev->dbi.command) dbi 606 drivers/gpu/drm/drm_mipi_dbi.c void mipi_dbi_hw_reset(struct mipi_dbi *dbi) dbi 608 drivers/gpu/drm/drm_mipi_dbi.c if (!dbi->reset) dbi 611 drivers/gpu/drm/drm_mipi_dbi.c gpiod_set_value_cansleep(dbi->reset, 0); dbi 613 drivers/gpu/drm/drm_mipi_dbi.c gpiod_set_value_cansleep(dbi->reset, 1); dbi 630 drivers/gpu/drm/drm_mipi_dbi.c bool mipi_dbi_display_is_on(struct mipi_dbi *dbi) dbi 634 drivers/gpu/drm/drm_mipi_dbi.c if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val)) dbi 653 drivers/gpu/drm/drm_mipi_dbi.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 664 drivers/gpu/drm/drm_mipi_dbi.c if (cond && mipi_dbi_display_is_on(dbi)) dbi 667 drivers/gpu/drm/drm_mipi_dbi.c mipi_dbi_hw_reset(dbi); dbi 668 drivers/gpu/drm/drm_mipi_dbi.c ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET); dbi 681 drivers/gpu/drm/drm_mipi_dbi.c if (dbi->reset) dbi 770 drivers/gpu/drm/drm_mipi_dbi.c static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc, dbi 775 drivers/gpu/drm/drm_mipi_dbi.c size_t chunk, max_chunk = dbi->tx_buf9_len; dbi 776 drivers/gpu/drm/drm_mipi_dbi.c struct spi_device *spi = dbi->spi; dbi 778 drivers/gpu/drm/drm_mipi_dbi.c .tx_buf = dbi->tx_buf9, dbi 798 drivers/gpu/drm/drm_mipi_dbi.c dst = dbi->tx_buf9; dbi 818 drivers/gpu/drm/drm_mipi_dbi.c dst = dbi->tx_buf9; dbi 888 drivers/gpu/drm/drm_mipi_dbi.c static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc, dbi 892 drivers/gpu/drm/drm_mipi_dbi.c struct spi_device *spi = dbi->spi; dbi 904 drivers/gpu/drm/drm_mipi_dbi.c return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw); dbi 907 drivers/gpu/drm/drm_mipi_dbi.c max_chunk = dbi->tx_buf9_len; dbi 908 drivers/gpu/drm/drm_mipi_dbi.c dst16 = dbi->tx_buf9; dbi 951 drivers/gpu/drm/drm_mipi_dbi.c static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, dbi 957 drivers/gpu/drm/drm_mipi_dbi.c if (mipi_dbi_command_is_read(dbi, *cmd)) dbi 962 drivers/gpu/drm/drm_mipi_dbi.c ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8); dbi 966 drivers/gpu/drm/drm_mipi_dbi.c return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw); dbi 971 drivers/gpu/drm/drm_mipi_dbi.c static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, dbi 974 drivers/gpu/drm/drm_mipi_dbi.c struct spi_device *spi = dbi->spi; dbi 1011 drivers/gpu/drm/drm_mipi_dbi.c gpiod_set_value_cansleep(dbi->dc, 0); dbi 1035 drivers/gpu/drm/drm_mipi_dbi.c static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, dbi 1038 drivers/gpu/drm/drm_mipi_dbi.c struct spi_device *spi = dbi->spi; dbi 1043 drivers/gpu/drm/drm_mipi_dbi.c if (mipi_dbi_command_is_read(dbi, *cmd)) dbi 1044 drivers/gpu/drm/drm_mipi_dbi.c return mipi_dbi_typec3_command_read(dbi, cmd, par, num); dbi 1048 drivers/gpu/drm/drm_mipi_dbi.c gpiod_set_value_cansleep(dbi->dc, 0); dbi 1054 drivers/gpu/drm/drm_mipi_dbi.c if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes) dbi 1057 drivers/gpu/drm/drm_mipi_dbi.c gpiod_set_value_cansleep(dbi->dc, 1); dbi 1085 drivers/gpu/drm/drm_mipi_dbi.c int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, dbi 1109 drivers/gpu/drm/drm_mipi_dbi.c dbi->spi = spi; dbi 1110 drivers/gpu/drm/drm_mipi_dbi.c dbi->read_commands = mipi_dbi_dcs_read_commands; dbi 1113 drivers/gpu/drm/drm_mipi_dbi.c dbi->command = mipi_dbi_typec3_command; dbi 1114 drivers/gpu/drm/drm_mipi_dbi.c dbi->dc = dc; dbi 1116 drivers/gpu/drm/drm_mipi_dbi.c dbi->swap_bytes = true; dbi 1118 drivers/gpu/drm/drm_mipi_dbi.c dbi->command = mipi_dbi_typec1_command; dbi 1119 drivers/gpu/drm/drm_mipi_dbi.c dbi->tx_buf9_len = SZ_16K; dbi 1120 drivers/gpu/drm/drm_mipi_dbi.c dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL); dbi 1121 drivers/gpu/drm/drm_mipi_dbi.c if (!dbi->tx_buf9) dbi 1125 drivers/gpu/drm/drm_mipi_dbi.c mutex_init(&dbi->cmdlock); dbi 1231 drivers/gpu/drm/drm_mipi_dbi.c ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i); dbi 1244 drivers/gpu/drm/drm_mipi_dbi.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 1253 drivers/gpu/drm/drm_mipi_dbi.c if (!mipi_dbi_command_is_read(dbi, cmd)) dbi 1273 drivers/gpu/drm/drm_mipi_dbi.c ret = mipi_dbi_command_buf(dbi, cmd, val, len); dbi 1318 drivers/gpu/drm/drm_mipi_dbi.c if (dbidev->dbi.read_commands) dbi 51 drivers/gpu/drm/tiny/hx8357d.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 67 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETEXTC, 0xFF, 0x83, 0x57); dbi 71 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETRGB, 0x00, 0x00, 0x06, 0x06); dbi 74 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETCOM, 0x25); dbi 77 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETOSC, 0x68); dbi 80 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETPANEL, 0x05); dbi 82 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETPOWER, dbi 90 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETSTBA, dbi 98 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETCYC, dbi 107 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, HX8357D_SETGAMMA, dbi 144 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, dbi 148 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_ON, 0x00); dbi 151 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_SCANLINE, 0x00, 0x02); dbi 154 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); dbi 158 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); dbi 176 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); dbi 254 drivers/gpu/drm/tiny/hx8357d.c ret = mipi_dbi_spi_init(spi, &dbidev->dbi, dc); dbi 71 drivers/gpu/drm/tiny/ili9225.c static inline int ili9225_command(struct mipi_dbi *dbi, u8 cmd, u16 data) dbi 75 drivers/gpu/drm/tiny/ili9225.c return mipi_dbi_command_buf(dbi, cmd, par, 2); dbi 84 drivers/gpu/drm/tiny/ili9225.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 85 drivers/gpu/drm/tiny/ili9225.c bool swap = dbi->swap_bytes; dbi 102 drivers/gpu/drm/tiny/ili9225.c if (!dbi->dc || !full || swap || dbi 147 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_HORIZ_WINDOW_ADDR_1, x2); dbi 148 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_HORIZ_WINDOW_ADDR_2, x1); dbi 149 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_VERT_WINDOW_ADDR_1, y2); dbi 150 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_VERT_WINDOW_ADDR_2, y1); dbi 152 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_1, x_start); dbi 153 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_2, y_start); dbi 155 drivers/gpu/drm/tiny/ili9225.c ret = mipi_dbi_command_buf(dbi, ILI9225_WRITE_DATA_TO_GRAM, tr, dbi 189 drivers/gpu/drm/tiny/ili9225.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 204 drivers/gpu/drm/tiny/ili9225.c mipi_dbi_hw_reset(dbi); dbi 212 drivers/gpu/drm/tiny/ili9225.c ret = ili9225_command(dbi, ILI9225_POWER_CONTROL_1, 0x0000); dbi 217 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x0000); dbi 218 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_3, 0x0000); dbi 219 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_4, 0x0000); dbi 220 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_5, 0x0000); dbi 224 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x0018); dbi 225 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_3, 0x6121); dbi 226 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_4, 0x006f); dbi 227 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_5, 0x495f); dbi 228 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_1, 0x0800); dbi 232 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x103b); dbi 250 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_DRIVER_OUTPUT_CONTROL, 0x011c); dbi 251 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_LCD_AC_DRIVING_CONTROL, 0x0100); dbi 252 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_ENTRY_MODE, 0x1000 | am_id); dbi 253 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x0000); dbi 254 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_BLANK_PERIOD_CONTROL_1, 0x0808); dbi 255 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_FRAME_CYCLE_CONTROL, 0x1100); dbi 256 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_INTERFACE_CONTROL, 0x0000); dbi 257 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_OSCILLATION_CONTROL, 0x0d01); dbi 258 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_VCI_RECYCLING, 0x0020); dbi 259 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_1, 0x0000); dbi 260 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_2, 0x0000); dbi 262 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GATE_SCAN_CONTROL, 0x0000); dbi 263 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_VERTICAL_SCROLL_1, 0x00db); dbi 264 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_VERTICAL_SCROLL_2, 0x0000); dbi 265 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_VERTICAL_SCROLL_3, 0x0000); dbi 266 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_PARTIAL_DRIVING_POS_1, 0x00db); dbi 267 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_PARTIAL_DRIVING_POS_2, 0x0000); dbi 269 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_1, 0x0000); dbi 270 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_2, 0x0808); dbi 271 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_3, 0x080a); dbi 272 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_4, 0x000a); dbi 273 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_5, 0x0a08); dbi 274 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_6, 0x0808); dbi 275 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_7, 0x0000); dbi 276 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_8, 0x0a00); dbi 277 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_9, 0x0710); dbi 278 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_GAMMA_CONTROL_10, 0x0710); dbi 280 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x0012); dbi 284 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x1017); dbi 295 drivers/gpu/drm/tiny/ili9225.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 309 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x0000); dbi 311 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x0007); dbi 313 drivers/gpu/drm/tiny/ili9225.c ili9225_command(dbi, ILI9225_POWER_CONTROL_1, 0x0a02); dbi 318 drivers/gpu/drm/tiny/ili9225.c static int ili9225_dbi_command(struct mipi_dbi *dbi, u8 *cmd, u8 *par, dbi 321 drivers/gpu/drm/tiny/ili9225.c struct spi_device *spi = dbi->spi; dbi 326 drivers/gpu/drm/tiny/ili9225.c gpiod_set_value_cansleep(dbi->dc, 0); dbi 332 drivers/gpu/drm/tiny/ili9225.c if (*cmd == ILI9225_WRITE_DATA_TO_GRAM && !dbi->swap_bytes) dbi 335 drivers/gpu/drm/tiny/ili9225.c gpiod_set_value_cansleep(dbi->dc, 1); dbi 383 drivers/gpu/drm/tiny/ili9225.c struct mipi_dbi *dbi; dbi 392 drivers/gpu/drm/tiny/ili9225.c dbi = &dbidev->dbi; dbi 402 drivers/gpu/drm/tiny/ili9225.c dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); dbi 403 drivers/gpu/drm/tiny/ili9225.c if (IS_ERR(dbi->reset)) { dbi 405 drivers/gpu/drm/tiny/ili9225.c return PTR_ERR(dbi->reset); dbi 416 drivers/gpu/drm/tiny/ili9225.c ret = mipi_dbi_spi_init(spi, dbi, rs); dbi 421 drivers/gpu/drm/tiny/ili9225.c dbi->command = ili9225_dbi_command; dbi 57 drivers/gpu/drm/tiny/ili9341.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 72 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF); dbi 74 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_PWCTRLB, 0x00, 0xc1, 0x30); dbi 75 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81); dbi 76 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_DTCTRLA, 0x85, 0x00, 0x78); dbi 77 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02); dbi 78 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_PUMPCTRL, 0x20); dbi 79 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_DTCTRLB, 0x00, 0x00); dbi 82 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_PWCTRL1, 0x23); dbi 83 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_PWCTRL2, 0x10); dbi 85 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_VMCTRL1, 0x3e, 0x28); dbi 86 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_VMCTRL2, 0x86); dbi 89 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); dbi 92 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_FRMCTR1, 0x00, 0x1b); dbi 95 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_EN3GAM, 0x00); dbi 96 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01); dbi 97 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_PGAMCTRL, dbi 100 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_NGAMCTRL, dbi 105 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_ETMOD, 0x07); dbi 108 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, ILI9341_DISCTRL, 0x08, 0x82, 0x27, 0x00); dbi 109 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); dbi 112 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); dbi 132 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); dbi 181 drivers/gpu/drm/tiny/ili9341.c struct mipi_dbi *dbi; dbi 190 drivers/gpu/drm/tiny/ili9341.c dbi = &dbidev->dbi; dbi 200 drivers/gpu/drm/tiny/ili9341.c dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); dbi 201 drivers/gpu/drm/tiny/ili9341.c if (IS_ERR(dbi->reset)) { dbi 203 drivers/gpu/drm/tiny/ili9341.c return PTR_ERR(dbi->reset); dbi 218 drivers/gpu/drm/tiny/ili9341.c ret = mipi_dbi_spi_init(spi, dbi, dc); dbi 55 drivers/gpu/drm/tiny/mi0283qt.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 70 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF); dbi 72 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_PWCTRLB, 0x00, 0x83, 0x30); dbi 73 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81); dbi 74 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_DTCTRLA, 0x85, 0x01, 0x79); dbi 75 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02); dbi 76 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_PUMPCTRL, 0x20); dbi 77 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_DTCTRLB, 0x00, 0x00); dbi 80 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_PWCTRL1, 0x26); dbi 81 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_PWCTRL2, 0x11); dbi 83 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_VMCTRL1, 0x35, 0x3e); dbi 84 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_VMCTRL2, 0xbe); dbi 87 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); dbi 90 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_FRMCTR1, 0x00, 0x1b); dbi 93 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_EN3GAM, 0x08); dbi 94 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01); dbi 95 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_PGAMCTRL, dbi 98 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_NGAMCTRL, dbi 103 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_ETMOD, 0x07); dbi 106 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, ILI9341_DISCTRL, 0x0a, 0x82, 0x27, 0x00); dbi 107 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); dbi 110 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); dbi 136 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); dbi 185 drivers/gpu/drm/tiny/mi0283qt.c struct mipi_dbi *dbi; dbi 194 drivers/gpu/drm/tiny/mi0283qt.c dbi = &dbidev->dbi; dbi 204 drivers/gpu/drm/tiny/mi0283qt.c dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); dbi 205 drivers/gpu/drm/tiny/mi0283qt.c if (IS_ERR(dbi->reset)) { dbi 207 drivers/gpu/drm/tiny/mi0283qt.c return PTR_ERR(dbi->reset); dbi 226 drivers/gpu/drm/tiny/mi0283qt.c ret = mipi_dbi_spi_init(spi, dbi, dc); dbi 118 drivers/gpu/drm/tiny/st7586.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 141 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, dbi 144 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, dbi 148 drivers/gpu/drm/tiny/st7586.c ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, dbi 182 drivers/gpu/drm/tiny/st7586.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 201 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_AUTO_READ_CTRL, 0x9f); dbi 202 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_OTP_RW_CTRL, 0x00); dbi 206 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_OTP_READ); dbi 210 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_OTP_CTRL_OUT); dbi 211 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); dbi 212 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF); dbi 216 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_SET_VOP_OFFSET, 0x00); dbi 217 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_SET_VOP, 0xe3, 0x00); dbi 218 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_SET_BIAS_SYSTEM, 0x02); dbi 219 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_SET_BOOST_LEVEL, 0x04); dbi 220 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_ENABLE_ANALOG, 0x1d); dbi 221 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_SET_NLINE_INV, 0x00); dbi 222 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_DISP_MODE_GRAY); dbi 223 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_ENABLE_DDRAM, 0x02); dbi 239 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); dbi 241 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_SET_DISP_DUTY, 0x7f); dbi 242 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, ST7586_SET_PART_DISP, 0xa0); dbi 243 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00, 0x77); dbi 244 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE); dbi 251 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); dbi 272 drivers/gpu/drm/tiny/st7586.c mipi_dbi_command(&dbidev->dbi, MIPI_DCS_SET_DISPLAY_OFF); dbi 323 drivers/gpu/drm/tiny/st7586.c struct mipi_dbi *dbi; dbi 333 drivers/gpu/drm/tiny/st7586.c dbi = &dbidev->dbi; dbi 345 drivers/gpu/drm/tiny/st7586.c dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); dbi 346 drivers/gpu/drm/tiny/st7586.c if (IS_ERR(dbi->reset)) { dbi 348 drivers/gpu/drm/tiny/st7586.c return PTR_ERR(dbi->reset); dbi 359 drivers/gpu/drm/tiny/st7586.c ret = mipi_dbi_spi_init(spi, dbi, a0); dbi 364 drivers/gpu/drm/tiny/st7586.c dbi->read_commands = NULL; dbi 379 drivers/gpu/drm/tiny/st7586.c dbi->swap_bytes = true; dbi 46 drivers/gpu/drm/tiny/st7735r.c struct mipi_dbi *dbi = &dbidev->dbi; dbi 61 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); dbi 64 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_FRMCTR1, 0x01, 0x2c, 0x2d); dbi 65 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_FRMCTR2, 0x01, 0x2c, 0x2d); dbi 66 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_FRMCTR3, 0x01, 0x2c, 0x2d, 0x01, 0x2c, dbi 68 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_INVCTR, 0x07); dbi 69 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_PWCTR1, 0xa2, 0x02, 0x84); dbi 70 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_PWCTR2, 0xc5); dbi 71 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_PWCTR3, 0x0a, 0x00); dbi 72 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_PWCTR4, 0x8a, 0x2a); dbi 73 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_PWCTR5, 0x8a, 0xee); dbi 74 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_VMCTR1, 0x0e); dbi 75 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE); dbi 90 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); dbi 91 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, dbi 93 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_GAMCTRP1, 0x02, 0x1c, 0x07, 0x12, 0x37, dbi 96 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, ST7735R_GAMCTRN1, 0x03, 0x1d, 0x07, 0x06, 0x2e, dbi 99 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); dbi 103 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_command(dbi, MIPI_DCS_ENTER_NORMAL_MODE); dbi 155 drivers/gpu/drm/tiny/st7735r.c struct mipi_dbi *dbi; dbi 164 drivers/gpu/drm/tiny/st7735r.c dbi = &dbidev->dbi; dbi 174 drivers/gpu/drm/tiny/st7735r.c dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); dbi 175 drivers/gpu/drm/tiny/st7735r.c if (IS_ERR(dbi->reset)) { dbi 177 drivers/gpu/drm/tiny/st7735r.c return PTR_ERR(dbi->reset); dbi 192 drivers/gpu/drm/tiny/st7735r.c ret = mipi_dbi_spi_init(spi, dbi, dc); dbi 197 drivers/gpu/drm/tiny/st7735r.c dbi->read_commands = NULL; dbi 196 drivers/net/ethernet/mellanox/mlx5/core/uar.c static unsigned long map_offset(struct mlx5_core_dev *mdev, int dbi) dbi 201 drivers/net/ethernet/mellanox/mlx5/core/uar.c return dbi / MLX5_BFREGS_PER_UAR * MLX5_ADAPTER_PAGE_SIZE + dbi 202 drivers/net/ethernet/mellanox/mlx5/core/uar.c (dbi % MLX5_BFREGS_PER_UAR) * dbi 215 drivers/net/ethernet/mellanox/mlx5/core/uar.c int dbi; dbi 244 drivers/net/ethernet/mellanox/mlx5/core/uar.c dbi = find_first_bit(bitmap, up->bfregs); dbi 245 drivers/net/ethernet/mellanox/mlx5/core/uar.c clear_bit(dbi, bitmap); dbi 250 drivers/net/ethernet/mellanox/mlx5/core/uar.c bfreg->map = up->map + map_offset(mdev, dbi); dbi 253 drivers/net/ethernet/mellanox/mlx5/core/uar.c bfreg->index = up->index + dbi / MLX5_BFREGS_PER_UAR; dbi 296 drivers/net/ethernet/mellanox/mlx5/core/uar.c unsigned int dbi; dbi 311 drivers/net/ethernet/mellanox/mlx5/core/uar.c dbi = addr_to_dbi_in_syspage(mdev, up, bfreg); dbi 312 drivers/net/ethernet/mellanox/mlx5/core/uar.c fp = (dbi % MLX5_BFREGS_PER_UAR) >= MLX5_NON_FP_BFREGS_PER_UAR; dbi 322 drivers/net/ethernet/mellanox/mlx5/core/uar.c set_bit(dbi, bitmap); dbi 153 drivers/pci/controller/dwc/pcie-kirin.c struct resource *dbi; dbi 165 drivers/pci/controller/dwc/pcie-kirin.c dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); dbi 166 drivers/pci/controller/dwc/pcie-kirin.c kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); dbi 179 drivers/target/target_core_user.c uint32_t *dbi; dbi 473 drivers/target/target_core_user.c #define tcmu_cmd_set_dbi(cmd, index) ((cmd)->dbi[(cmd)->dbi_cur++] = (index)) dbi 474 drivers/target/target_core_user.c #define tcmu_cmd_get_dbi(cmd) ((cmd)->dbi[(cmd)->dbi_cur++]) dbi 482 drivers/target/target_core_user.c clear_bit(tcmu_cmd->dbi[i], udev->data_bitmap); dbi 489 drivers/target/target_core_user.c int ret, dbi; dbi 491 drivers/target/target_core_user.c dbi = find_first_zero_bit(udev->data_bitmap, udev->dbi_thresh); dbi 492 drivers/target/target_core_user.c if (dbi == udev->dbi_thresh) dbi 495 drivers/target/target_core_user.c page = radix_tree_lookup(&udev->data_blocks, dbi); dbi 506 drivers/target/target_core_user.c ret = radix_tree_insert(&udev->data_blocks, dbi, page); dbi 511 drivers/target/target_core_user.c if (dbi > udev->dbi_max) dbi 512 drivers/target/target_core_user.c udev->dbi_max = dbi; dbi 514 drivers/target/target_core_user.c set_bit(dbi, udev->data_bitmap); dbi 515 drivers/target/target_core_user.c tcmu_cmd_set_dbi(tcmu_cmd, dbi); dbi 538 drivers/target/target_core_user.c tcmu_get_block_page(struct tcmu_dev *udev, uint32_t dbi) dbi 540 drivers/target/target_core_user.c return radix_tree_lookup(&udev->data_blocks, dbi); dbi 545 drivers/target/target_core_user.c kfree(tcmu_cmd->dbi); dbi 586 drivers/target/target_core_user.c tcmu_cmd->dbi = kcalloc(tcmu_cmd->dbi_cnt, sizeof(uint32_t), dbi 588 drivers/target/target_core_user.c if (!tcmu_cmd->dbi) { dbi 651 drivers/target/target_core_user.c int dbi, int remaining) dbi 653 drivers/target/target_core_user.c return dev->data_off + dbi * DATA_BLOCK_SIZE + dbi 667 drivers/target/target_core_user.c int i, dbi; dbi 683 drivers/target/target_core_user.c dbi = tcmu_cmd_get_dbi(tcmu_cmd); dbi 684 drivers/target/target_core_user.c page = tcmu_get_block_page(udev, dbi); dbi 691 drivers/target/target_core_user.c to_offset = get_block_offset_user(udev, dbi, dbi 742 drivers/target/target_core_user.c int i, dbi; dbi 778 drivers/target/target_core_user.c dbi = tcmu_cmd_get_dbi(cmd); dbi 779 drivers/target/target_core_user.c page = tcmu_get_block_page(udev, dbi); dbi 1503 drivers/target/target_core_user.c static struct page *tcmu_try_get_block_page(struct tcmu_dev *udev, uint32_t dbi) dbi 1508 drivers/target/target_core_user.c page = tcmu_get_block_page(udev, dbi); dbi 1519 drivers/target/target_core_user.c dbi, udev->name); dbi 1549 drivers/target/target_core_user.c uint32_t dbi; dbi 1552 drivers/target/target_core_user.c dbi = (offset - udev->data_off) / DATA_BLOCK_SIZE; dbi 1553 drivers/target/target_core_user.c page = tcmu_try_get_block_page(udev, dbi); dbi 32 include/drm/drm_mipi_dbi.h int (*command)(struct mipi_dbi *dbi, u8 *cmd, u8 *param, size_t num); dbi 125 include/drm/drm_mipi_dbi.h struct mipi_dbi dbi; dbi 133 include/drm/drm_mipi_dbi.h int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, dbi 150 include/drm/drm_mipi_dbi.h void mipi_dbi_hw_reset(struct mipi_dbi *dbi); dbi 151 include/drm/drm_mipi_dbi.h bool mipi_dbi_display_is_on(struct mipi_dbi *dbi); dbi 159 include/drm/drm_mipi_dbi.h int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val); dbi 160 include/drm/drm_mipi_dbi.h int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len); dbi 161 include/drm/drm_mipi_dbi.h int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len); dbi 176 include/drm/drm_mipi_dbi.h #define mipi_dbi_command(dbi, cmd, seq...) \ dbi 179 include/drm/drm_mipi_dbi.h mipi_dbi_command_stackbuf(dbi, cmd, d, ARRAY_SIZE(d)); \