DPP_CONTROL        99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_GET(DPP_CONTROL,
DPP_CONTROL       511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 			REG_UPDATE_2(DPP_CONTROL,
DPP_CONTROL       515 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 			REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
DPP_CONTROL       517 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
DPP_CONTROL       123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DPP_CONTROL, DPP_TOP, id), \
DPP_CONTROL      1336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t DPP_CONTROL; \
DPP_CONTROL        56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_GET(DPP_CONTROL,