DPPCLK_DTO_PARAM   69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_GET_2(DPPCLK_DTO_PARAM[dpp_inst],
DPPCLK_DTO_PARAM   76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
DPPCLK_DTO_PARAM   80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
DPPCLK_DTO_PARAM   85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
DPPCLK_DTO_PARAM   89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	uint32_t DPPCLK_DTO_PARAM[6];