DPPCLK_DTO_CTRL    90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL,
DPPCLK_DTO_CTRL    93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL,
DPPCLK_DTO_CTRL   127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1);
DPPCLK_DTO_CTRL   130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1);
DPPCLK_DTO_CTRL   133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1);
DPPCLK_DTO_CTRL   136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1);
DPPCLK_DTO_CTRL   139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1);
DPPCLK_DTO_CTRL   142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1);
DPPCLK_DTO_CTRL    32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	SR(DPPCLK_DTO_CTRL),\
DPPCLK_DTO_CTRL    51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
DPPCLK_DTO_CTRL    52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
DPPCLK_DTO_CTRL    53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
DPPCLK_DTO_CTRL    54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
DPPCLK_DTO_CTRL    55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
DPPCLK_DTO_CTRL    56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
DPPCLK_DTO_CTRL    57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
DPPCLK_DTO_CTRL    58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
DPPCLK_DTO_CTRL    66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
DPPCLK_DTO_CTRL    67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
DPPCLK_DTO_CTRL    68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
DPPCLK_DTO_CTRL    69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh)
DPPCLK_DTO_CTRL    88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 	uint32_t DPPCLK_DTO_CTRL;