db_mask 367 drivers/ntb/hw/amd/ntb_hw_amd.c ndev->db_mask |= db_bits; db_mask 368 drivers/ntb/hw/amd/ntb_hw_amd.c writew((u16)ndev->db_mask, mmio + AMD_DBMASK_OFFSET); db_mask 384 drivers/ntb/hw/amd/ntb_hw_amd.c ndev->db_mask &= ~db_bits; db_mask 385 drivers/ntb/hw/amd/ntb_hw_amd.c writew((u16)ndev->db_mask, mmio + AMD_DBMASK_OFFSET); db_mask 592 drivers/ntb/hw/amd/ntb_hw_amd.c ndev->db_mask = ndev->db_valid_mask; db_mask 692 drivers/ntb/hw/amd/ntb_hw_amd.c ndev->db_mask = ndev->db_valid_mask; db_mask 693 drivers/ntb/hw/amd/ntb_hw_amd.c writel(ndev->db_mask, mmio + AMD_DBMASK_OFFSET); db_mask 198 drivers/ntb/hw/amd/ntb_hw_amd.h u64 db_mask; db_mask 237 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->db_mask |= db_bits; db_mask 238 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, mmio); db_mask 258 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->db_mask &= ~db_bits; db_mask 259 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, mmio); db_mask 374 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->db_mask = ndev->db_valid_mask; db_mask 375 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, db_mask 377 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->self_reg->db_mask); db_mask 471 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->db_mask = ndev->db_valid_mask; db_mask 472 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, db_mask 474 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->self_reg->db_mask); db_mask 566 drivers/ntb/hw/intel/ntb_hw_gen1.c "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask); db_mask 568 drivers/ntb/hw/intel/ntb_hw_gen1.c u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); db_mask 1100 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->self_reg->db_mask); db_mask 1109 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->self_reg->db_mask); db_mask 1635 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->self_reg->db_mask); db_mask 1849 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->db_mask = 0; db_mask 1952 drivers/ntb/hw/intel/ntb_hw_gen1.c .db_mask = XEON_PDBMSK_OFFSET, db_mask 1958 drivers/ntb/hw/intel/ntb_hw_gen1.c .db_mask = XEON_SDBMSK_OFFSET, db_mask 76 drivers/ntb/hw/intel/ntb_hw_gen3.c .db_mask = GEN3_IM_INT_DISABLE_OFFSET, db_mask 83 drivers/ntb/hw/intel/ntb_hw_gen3.c .db_mask = GEN3_EM_INT_DISABLE_OFFSET, db_mask 221 drivers/ntb/hw/intel/ntb_hw_gen3.c ndev->self_reg->db_mask); db_mask 318 drivers/ntb/hw/intel/ntb_hw_gen3.c "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask); db_mask 320 drivers/ntb/hw/intel/ntb_hw_gen3.c u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); db_mask 114 drivers/ntb/hw/intel/ntb_hw_intel.h unsigned long db_mask; db_mask 160 drivers/ntb/hw/intel/ntb_hw_intel.h u64 db_mask; db_mask 69 drivers/ntb/hw/mscc/ntb_hw_switchtec.c u64 db_mask; db_mask 652 drivers/ntb/hw/mscc/ntb_hw_switchtec.c sndev->db_mask |= db_bits << sndev->db_shift; db_mask 653 drivers/ntb/hw/mscc/ntb_hw_switchtec.c iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); db_mask 670 drivers/ntb/hw/mscc/ntb_hw_switchtec.c sndev->db_mask &= ~(db_bits << sndev->db_shift); db_mask 671 drivers/ntb/hw/mscc/ntb_hw_switchtec.c iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); db_mask 682 drivers/ntb/hw/mscc/ntb_hw_switchtec.c return (sndev->db_mask >> sndev->db_shift) & sndev->db_valid_mask; db_mask 1236 drivers/ntb/hw/mscc/ntb_hw_switchtec.c sndev->db_mask = 0x0FFFFFFFFFFFFFFFULL; db_mask 1241 drivers/ntb/hw/mscc/ntb_hw_switchtec.c sndev->db_valid_mask = sndev->db_mask; db_mask 1252 drivers/ntb/hw/mscc/ntb_hw_switchtec.c iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); db_mask 316 drivers/ntb/test/ntb_pingpong.c u64 db_mask, msg_mask; db_mask 319 drivers/ntb/test/ntb_pingpong.c db_mask = ntb_db_valid_mask(pp->ntb); db_mask 320 drivers/ntb/test/ntb_pingpong.c ret = ntb_db_set_mask(pp->ntb, db_mask); db_mask 307 drivers/ntb/test/ntb_tool.c u64 db_bits, db_mask; db_mask 309 drivers/ntb/test/ntb_tool.c db_mask = ntb_db_vector_mask(tc->ntb, vec); db_mask 313 drivers/ntb/test/ntb_tool.c vec, db_mask, db_bits);