db_cacheline       57 drivers/gpu/drm/i915/gt/uc/intel_guc.h 	u32 db_cacheline;
db_cacheline      263 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	offset = offset_in_page(guc->db_cacheline);
db_cacheline      266 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	guc->db_cacheline += cache_line_size();
db_cacheline      269 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 			 offset, guc->db_cacheline, cache_line_size());
db_cacheline     1899 drivers/gpu/drm/i915/i915_debugfs.c 	seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline);