DPG_RAMP_CONTROL  203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_SET_3(DPG_RAMP_CONTROL, 0,
DPG_RAMP_CONTROL  214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_SET_3(DPG_RAMP_CONTROL, 0,
DPG_RAMP_CONTROL  225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_SET_3(DPG_RAMP_CONTROL, 0,
DPG_RAMP_CONTROL  252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		REG_WRITE(DPG_RAMP_CONTROL, 0);
DPG_RAMP_CONTROL   42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_RAMP_CONTROL, DPG, id), \
DPG_RAMP_CONTROL   59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	uint32_t DPG_RAMP_CONTROL; \