DPG_PIPE_URGENCY_CONTROL 1123 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); DPG_PIPE_URGENCY_CONTROL 1124 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); DPG_PIPE_URGENCY_CONTROL 1130 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); DPG_PIPE_URGENCY_CONTROL 1131 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); DPG_PIPE_URGENCY_CONTROL 1149 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); DPG_PIPE_URGENCY_CONTROL 1150 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); DPG_PIPE_URGENCY_CONTROL 1156 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); DPG_PIPE_URGENCY_CONTROL 1157 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); DPG_PIPE_URGENCY_CONTROL 172 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, DPG_PIPE_URGENCY_CONTROL 186 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, DPG_PIPE_URGENCY_CONTROL 53 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\ DPG_PIPE_URGENCY_CONTROL 108 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_URGENCY_CONTROL; DPG_PIPE_URGENCY_CONTROL 179 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ DPG_PIPE_URGENCY_CONTROL 180 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ DPG_PIPE_URGENCY_CONTROL 220 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ DPG_PIPE_URGENCY_CONTROL 221 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\