DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 201 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) { DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 205 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 210 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 63 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id) DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 110 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL; DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 189 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\ DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 190 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 191 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 192 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)