DPG_PIPE_LOW_POWER_CONTROL  214 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {
DPG_PIPE_LOW_POWER_CONTROL  218 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE_3(DPG_PIPE_LOW_POWER_CONTROL,
DPG_PIPE_LOW_POWER_CONTROL  223 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 		REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,
DPG_PIPE_LOW_POWER_CONTROL   78 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\
DPG_PIPE_LOW_POWER_CONTROL  111 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	uint32_t DPG_PIPE_LOW_POWER_CONTROL;
DPG_PIPE_LOW_POWER_CONTROL  223 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
DPG_PIPE_LOW_POWER_CONTROL  224 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
DPG_PIPE_LOW_POWER_CONTROL  225 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
DPG_PIPE_LOW_POWER_CONTROL  226 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)