DPG_CONTROL       103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		REG_UPDATE_6(DPG_CONTROL,
DPG_CONTROL       162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		REG_UPDATE_6(DPG_CONTROL,
DPG_CONTROL       207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_UPDATE_2(DPG_CONTROL,
DPG_CONTROL       218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_UPDATE_2(DPG_CONTROL,
DPG_CONTROL       229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 			REG_UPDATE_2(DPG_CONTROL,
DPG_CONTROL       239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		REG_UPDATE_4(DPG_CONTROL,
DPG_CONTROL       248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		REG_WRITE(DPG_CONTROL, 0);
DPG_CONTROL       258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		REG_UPDATE_2(DPG_CONTROL,
DPG_CONTROL       298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	REG_GET_2(DPG_CONTROL,
DPG_CONTROL        37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_CONTROL, DPG, id), \
DPG_CONTROL        54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	uint32_t DPG_CONTROL; \