DP0_DP_SEC_CNTL   237 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   238 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   239 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   240 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   241 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   242 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   278 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   279 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   280 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   281 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   327 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   352 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   353 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   354 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   355 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
DP0_DP_SEC_CNTL   285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\