DOMAIN5_PG_STATUS  202 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN5_PG_STATUS), \
DOMAIN5_PG_STATUS  258 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN5_PG_STATUS), \
DOMAIN5_PG_STATUS  318 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN5_PG_STATUS), \
DOMAIN5_PG_STATUS  387 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t DOMAIN5_PG_STATUS;
DOMAIN5_PG_STATUS  568 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN5_PG_STATUS  625 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN5_PG_STATUS  675 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN5_PG_STATUS  530 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_WAIT(DOMAIN5_PG_STATUS,
DOMAIN5_PG_STATUS  359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_WAIT(DOMAIN5_PG_STATUS,