DOMAIN4_PG_STATUS 201 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_STATUS), \ DOMAIN4_PG_STATUS 257 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_STATUS), \ DOMAIN4_PG_STATUS 317 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_STATUS), \ DOMAIN4_PG_STATUS 386 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN4_PG_STATUS; DOMAIN4_PG_STATUS 567 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ DOMAIN4_PG_STATUS 624 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ DOMAIN4_PG_STATUS 674 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ DOMAIN4_PG_STATUS 582 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_WAIT(DOMAIN4_PG_STATUS, DOMAIN4_PG_STATUS 433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_WAIT(DOMAIN4_PG_STATUS,