DOMAIN3_PG_STATUS  200 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN3_PG_STATUS), \
DOMAIN3_PG_STATUS  256 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN3_PG_STATUS), \
DOMAIN3_PG_STATUS  316 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN3_PG_STATUS), \
DOMAIN3_PG_STATUS  385 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t DOMAIN3_PG_STATUS;
DOMAIN3_PG_STATUS  566 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN3_PG_STATUS  623 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN3_PG_STATUS  673 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN3_PG_STATUS  522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_WAIT(DOMAIN3_PG_STATUS,
DOMAIN3_PG_STATUS  351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_WAIT(DOMAIN3_PG_STATUS,