DOMAIN21_PG_STATUS  270 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN21_PG_STATUS), \
DOMAIN21_PG_STATUS  399 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t DOMAIN21_PG_STATUS;
DOMAIN21_PG_STATUS  637 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN21_PG_STATUS  311 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_WAIT(DOMAIN21_PG_STATUS,