DOMAIN1_PG_STATUS  198 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN1_PG_STATUS), \
DOMAIN1_PG_STATUS  254 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN1_PG_STATUS), \
DOMAIN1_PG_STATUS  314 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DOMAIN1_PG_STATUS), \
DOMAIN1_PG_STATUS  383 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t DOMAIN1_PG_STATUS;
DOMAIN1_PG_STATUS  564 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN1_PG_STATUS  621 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN1_PG_STATUS  671 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
DOMAIN1_PG_STATUS  514 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_WAIT(DOMAIN1_PG_STATUS,
DOMAIN1_PG_STATUS  343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_WAIT(DOMAIN1_PG_STATUS,