DOMAIN0_PG_CONFIG 189 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_CONFIG), \ DOMAIN0_PG_CONFIG 235 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_CONFIG), \ DOMAIN0_PG_CONFIG 302 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_CONFIG), \ DOMAIN0_PG_CONFIG 364 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DOMAIN0_PG_CONFIG; DOMAIN0_PG_CONFIG 547 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ DOMAIN0_PG_CONFIG 548 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ DOMAIN0_PG_CONFIG 584 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ DOMAIN0_PG_CONFIG 585 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ DOMAIN0_PG_CONFIG 648 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ DOMAIN0_PG_CONFIG 649 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ DOMAIN0_PG_CONFIG 451 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); DOMAIN0_PG_CONFIG 558 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (REG(DOMAIN0_PG_CONFIG) == 0) DOMAIN0_PG_CONFIG 563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_PG_CONFIG 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); DOMAIN0_PG_CONFIG 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN0_PG_CONFIG) == 0) DOMAIN0_PG_CONFIG 414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN0_PG_CONFIG,