DMU_MEM_PWR_CNTL  332 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
DMU_MEM_PWR_CNTL  453 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
DMU_MEM_PWR_CNTL  494 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
DMU_MEM_PWR_CNTL   72 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	SR(DMU_MEM_PWR_CNTL)
DMU_MEM_PWR_CNTL  128 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(DMU_MEM_PWR_CNTL, \
DMU_MEM_PWR_CNTL  164 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	uint32_t DMU_MEM_PWR_CNTL;
DMU_MEM_PWR_CNTL  125 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DMU_MEM_PWR_CNTL;