DMU_BASE           44 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
DMU_BASE           44 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
DMU_BASE           67 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
DMU_BASE           67 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
DMU_BASE           81 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },