DME_CONTROL       169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DME_CONTROL;
DME_CONTROL       381 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE_2(DME_CONTROL,
DME_CONTROL       404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DME_CONTROL,
DME_CONTROL       407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 		REG_UPDATE(DME_CONTROL,
DME_CONTROL        39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(DME_CONTROL, DIG, id),\