DMCU_IRAM_RD_CTRL  108 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
DMCU_IRAM_RD_CTRL  335 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
DMCU_IRAM_RD_CTRL  497 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
DMCU_IRAM_RD_CTRL   43 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	SR(DMCU_IRAM_RD_CTRL), \
DMCU_IRAM_RD_CTRL   60 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	SR(DMCU_IRAM_RD_CTRL), \
DMCU_IRAM_RD_CTRL  173 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	uint32_t DMCU_IRAM_RD_CTRL;
DMCU_IRAM_RD_CTRL   48 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SR(DMCU_IRAM_RD_CTRL), \
DMCU_IRAM_RD_CTRL  126 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DMCU_IRAM_RD_CTRL;