d71 341 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_layer_init(struct d71_dev *d71, d71 349 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*layer), d71 368 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&layer->hsize_in, 4, d71->max_line_size); d71 369 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&layer->vsize_in, 4, d71->max_vsize); d71 438 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_wb_layer_init(struct d71_dev *d71, d71 447 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*wb_layer), d71 460 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&wb_layer->hsize_in, D71_MIN_LINE_SIZE, d71->max_line_size); d71 461 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&wb_layer->vsize_in, D71_MIN_VERTICAL_SIZE, d71->max_vsize); d71 577 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_compiz_init(struct d71_dev *d71, d71 586 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*compiz), d71 598 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&compiz->hsize, D71_MIN_LINE_SIZE, d71->max_line_size); d71 599 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&compiz->vsize, D71_MIN_VERTICAL_SIZE, d71->max_vsize); d71 734 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_scaler_init(struct d71_dev *d71, d71 743 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*scaler), d71 842 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_splitter_init(struct d71_dev *d71, d71 851 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*splitter), d71 865 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&splitter->hsize, 4, d71->max_line_size); d71 866 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&splitter->vsize, 4, d71->max_vsize); d71 912 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_merger_init(struct d71_dev *d71, d71 921 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*merger), d71 989 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_improc_init(struct d71_dev *d71, d71 998 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*improc), d71 1116 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static int d71_timing_ctrlr_init(struct d71_dev *d71, d71 1125 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*ctrlr), d71 1143 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c int d71_probe_block(struct d71_dev *d71, d71 1156 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe = d71->pipes[blk_id]; d71 1161 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_layer_init(d71, blk, reg); d71 1165 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_wb_layer_init(d71, blk, reg); d71 1169 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe = d71->pipes[blk_id]; d71 1171 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_compiz_init(d71, blk, reg); d71 1175 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_scaler_init(d71, blk, reg); d71 1179 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_splitter_init(d71, blk, reg); d71 1183 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_merger_init(d71, blk, reg); d71 1187 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe = d71->pipes[blk_id]; d71 1192 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_improc_init(d71, blk, reg); d71 1196 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe = d71->pipes[blk_id]; d71 1201 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_timing_ctrlr_init(d71, blk, reg); d71 1208 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c d71->glb_scl_coeff_addr[blk_id] = reg; d71 169 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 172 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS); d71 175 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c raw_status = malidp_read32(d71->gcu_addr, BLK_IRQ_RAW_STATUS); d71 181 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c status = malidp_read32(d71->gcu_addr, BLK_STATUS); d71 184 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(d71->gcu_addr, BLK_STATUS, d71 189 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32(d71->gcu_addr, BLK_IRQ_CLEAR, raw_status); d71 193 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status); d71 196 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status); d71 209 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 213 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, d71 215 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c for (i = 0; i < d71->num_pipelines; i++) { d71 216 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c pipe = d71->pipes[i]; d71 229 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 233 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, ENABLED_GCU_IRQS, 0); d71 234 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c for (i = 0; i < d71->num_pipelines; i++) { d71 235 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c pipe = d71->pipes[i]; d71 248 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 249 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_pipeline *pipe = d71->pipes[master_pipe]; d71 274 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 278 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode); d71 280 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) == opmode), d71 289 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 293 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL); d71 296 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c static int d71_reset(struct d71_dev *d71) d71 298 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *gcu = d71->gcu_addr; d71 329 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 331 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c if (!d71) d71 334 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c devm_kfree(mdev->dev, d71); d71 340 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71; d71 347 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71 = devm_kzalloc(mdev->dev, sizeof(*d71), GFP_KERNEL); d71 348 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c if (!d71) d71 351 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c mdev->chip_data = d71; d71 352 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->mdev = mdev; d71 353 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->gcu_addr = mdev->reg_base; d71 354 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->periph_addr = mdev->reg_base + (D71_BLOCK_OFFSET_PERIPH >> 2); d71 356 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c err = d71_reset(d71); d71 363 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c value = malidp_read32(d71->gcu_addr, GLB_CORE_INFO); d71 364 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->num_blocks = value & 0xFF; d71 365 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->num_pipelines = (value >> 8) & 0x7; d71 367 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c if (d71->num_pipelines > D71_MAX_PIPELINE) { d71 369 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c D71_MAX_PIPELINE, d71->num_pipelines); d71 375 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c value = malidp_read32(d71->periph_addr, BLK_BLOCK_INFO); d71 383 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c value = malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID); d71 385 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->max_line_size = value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048; d71 386 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->max_vsize = 4096; d71 387 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->num_rich_layers = value & PERIPH_NUM_RICH_LAYERS ? 2 : 1; d71 388 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->supports_dual_link = value & PERIPH_SPLIT_EN ? true : false; d71 389 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->integrates_tbu = value & PERIPH_TBU_EN ? true : false; d71 391 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c for (i = 0; i < d71->num_pipelines; i++) { d71 398 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71->pipes[i] = to_d71_pipeline(pipe); d71 404 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c while (i < d71->num_blocks) { d71 409 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c err = d71_probe_block(d71, &blk, blk_base); d71 419 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c i, d71->num_blocks); d71 518 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 519 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *reg = d71->gcu_addr; d71 520 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 check_bits = (d71->num_pipelines == 2) ? d71 524 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c if (!d71->integrates_tbu) d71 537 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c for (i = 0; i < d71->num_pipelines; i++) d71 538 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(d71->pipes[i]->lpu_addr, LPU_TBU_CONTROL, d71 545 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c struct d71_dev *d71 = mdev->chip_data; d71 546 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *reg = d71->gcu_addr; d71 547 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 check_bits = (d71->num_pipelines == 2) ? d71 48 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h int d71_probe_block(struct d71_dev *d71,