d4clk0            475 arch/mips/cavium-octeon/executive/cvmx-spi.c 		if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) {
d4clk0            482 arch/mips/cavium-octeon/executive/cvmx-spi.c 			stat.s.d4clk0 = 0;
d4clk0            489 arch/mips/cavium-octeon/executive/cvmx-spi.c 	} while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0);
d4clk0            122 arch/mips/include/asm/octeon/cvmx-spxx-defs.h 		uint64_t d4clk0:1;
d4clk0            126 arch/mips/include/asm/octeon/cvmx-spxx-defs.h 		uint64_t d4clk0:1;